4th ESO CCD Workshop Optical Detectors for Astronomy: Tuesday 1999-SEP-14: *

4th ESO CCD Workshop Optical Detectors for Astronomy: Wednesday 1999-SEP-15: *

4th ESO CCD Workshop Optical Detectors for Astronomy: Thursday 1999-SEP-16: *

• "May we turn very quickly around the (detector development) corner…

• Hamamatsu 2Kx4K CCD with 15um pixels, frontside: R&D at present
• Hamamatsu 3Kx6K CCD with 12um pixels: in future
• X-ray testing for CTE & amp noise & dark count, optical testing for linearity & QE
• MIT/LL, SITe, EEV & Hamamatsu CCDs tested
• MIT/LL wins for lowest read noise, MIT/LL high-rho CCDs win for relative QE
• EEV wins for full well
• SITe is poorest for flatness, sometimes flatness variation approaches 100um
• MFRONT electronics support circuits, with AC-coupled input with input clamp:
• www.messia.com for online info
• OPA627 opamp for preamp, DG403 clock drive analog switches
• Aluminum Nitride block under CCD
• Hamamatsu work:
• 2-phase 2-line MPP 2Kx4K with 15um pixels, 3-side buttable, direct FPC feed to MFRONT
• 10^5 e- full well, 3 e- rms read noise with 15usec pixels (twice the well of SITe)
• Suprime-Cam:
• 2x4 mosaic of 2Kx4K CCDs
• Cooled with Stirling-cycle cooler
• 4.5 Watts x2 @ -100C
• 2.5 minute readout time, limited by SITe CCDs, 35 sec for MIT/LL
• For future:
• Readout less than 30 seconds, higher blue QE, large(r) full well (>10^5 e-), fewer dead columns, smaller pixel size (10-12 um)
• Questions:
• QE’s are lab measured
• Stirling coolers need improvement
• MIT/LL backside: ion implant with laser anneal (6x6mm area) requires step & repeat, leaves a residual pattern on the backside, better than before, still more to improve

• VLT: one scope operational now
• Paranal: 77% photometric nights per year
• 30 of 2Kx4K CCDs on order
• 10 people in Garching & 4 in Chile on instrumentation team
• 2 DM per sec to operate each VLT scope => make CCDs read faster
• RQE measured in Garching:
• Lesser/Loral best for UV QE
• Read noise: 6 e- at 10^6 pixels/sec, goes down to 2 e- at 50x10^3 pixels/sec
• Cryostats:
• 48 hours autonomous operation standard
• Continuous-flow => 7 days autonomous operation, for fixed instruments only
• MIT/LL thick high-resistivity to be used
• Measuring machine can measure to 3um flatness over 16Kx16K detector area
• Questions:
• Buying 15um pixel CCDs
• 20 FIERA controllers delivered, more in progress
• CCD names: named prior to test, not personalities from tests

• CCD electronics for space:
• 1.1 watt power dissipation for electronics
• Radiation hardening required of parts
• Robotic-arm camera, present Mars mission:
• Only preamp near CCD
• Drive electronics 4 meters distant
• MVACS camera:
• 5 e- readout noise, 12-bit converter limits operation
• Frame-transfer CCD
• ACTEL gate arrays for sequencers
• OSIRIS:
• 4 cm resolution at 1km distance from nucleus
• 14-bit ADC dynamic range required, with 2 signal chains:
• 50000 e- unbinned
• 200000 e- binned
• 16-bit effective dynamic range
• EEV 13.5-micron 2Kx2K CCDs to be flown on narrow-angle camera
• AD590 temperature sensor, 160 Kelvin cold operating sensor, 140 Kelvin readable, in/on package
• During mission cruise, keep CCDs at +20C
• Cannot heat CCDs (for post-radiation anneal?)
• Concern about CTE degradation from radiation, tackle with shielding
• No questions

• Astroseismology: with 1 sec time resolution, star defocussed
• Exoplanet occultations:
• 3000 objects simultaneous down to mag 15.5
• 3-15 hour estimated transit times
• prism disperses light
• On-board data processing
• CCDs, EEV CCD42-80 back illuminated
• Frame-transfer on one CCD
• Questions disallowed

• OPTIC: 2 of 2Kx4K OTCCDs
• 2Kx2K HgCdTe HAWAII-2 IR arrays planned
• EEV 2Kx4.5K CCDs to be used (CCDs lengthened on wafer)
• No Questions
• Barry Starr:
• Megacam 18Kx18K with EEV 2Kx4.5K
• No Questions

• STJ detectors planned with ESA, first light earlier in 1999
• No questions

• Loral/Lesser, CatC (thin copper layer on backside for UV sensitization, immune to hydrogen) CCD

• No questions

• Currently, electronics removed from dewar vacuum, as prior boards in vacuum suspected as contamination source
• DC-coupled preamps for IR arrays, AC-coupled preamps for CCDs, essentially the same design

• Upgrading to LBNL high-resistivity 2Kx4K CCDs
• Getting 6 of Rockwill HgCdTe 2Kx2K imagers

• 6.5-meter primary aluminized in cell, on telescope
• 36 EEV 2Kx4K CCDs in Megacam (plus guider CCDs)

• Exponential growth of number of pixels in a mosaic focal plane versus linear time
• Over 90% shorts yields with 6 CCDs per 150-mm wafer, 50% scientific-grade yield
• Large arrays guarantee that there WILL be bloomed stars in ANY field
• Blooming control:
• Clocked antiblooming only works with imperfect devices, stops working as device quality approaches perfection
• Antiblooming structures will be required for higher-quality devices
• OTCCDs:
• Two of 1536Vx2048H OT image areas, two 512Vx2048H "frame store" guider areas
• OT clock phases now rearranged to be more symmetrical than initial design
• www.dmtelescope.org for Dark Matter telescope
• 3 x 3 degree field. 0.25 arcsecond per pixel scale
• Wide Field High Res Large Area Array:
• Perhaps 36 equivalent scopes, 1.5-m apertures, each scope with 1 x 1 degree field
• Cluster of computers stitch together areas from each scope looking at the same field
• Multiple OT cells per CCD proposed
• Software obviates matching focal lengths / image scales between telescopes (?!?)
• Questions:
• Do OT shifts yield clocked (dynamic) antiblooming inherently? Not yet studied.
• Can an antiblooming drain (post) be put in the corners of the pixels? Certainly more difficult, but not impossible.
• More details in a future paper to address the implementation issues.

• 2Kx4K EEV guiding/tracking CCD in focal plane
• Offset jumps (? Possibly from parallel clocking of multiple CCDs ?)
• 357Kpixels/sec with 4.5 e- noise @ 2 e-/ADU, CCD at 169 Kelvin, only one CCD output amp per chip used
• Questions:
• What is the cost? Not available at present.
• To scale up, what measures will be taken? Plan to automate test data collection, only semi-automated at present.
• With sharing of parallel clocks, were CCDs pretested for this? Not enough time, should be investigated.

• Integration into CFHT prime focus a big part of the process
• About 30-pixel spacing between CCDs (34 in X nominal, 32 in Y nominal)
• Noise mitigation:
• All CCDs independently wired
• Dewar electrically isolated from scope
• Questions:
• -88 C operation; what is dark current? A subsequent paper will address.

• 6.7 microseconds/pixel; integrator on-time 1 microsecond for each slope
• Dark current not a big concern compared to sky noise
• CCDs are good enough such that clocked antiblooming is not particularly effective, and pocket pumping not easy to remove, so clocked antiblooming is abandoned, but: the clocked antiblooming does remove residual image, so this is enabled between exposures
• Brick wall pattern not so much of a problem on more newly manufactured CCDs
• Fringing reduced by x10 using high-rho CCDs versus standard CCDs
• Questions:
• Were different clocking schemes tried to mitigate residual image? Yes, but antiblooming (dither) clocking was effective, so that as the way to go; parallel clock voltages were optimized for full well, but may be contributing to residual image due to populating surface states.

• Questions:
• Star tracks stay lined with columns; precession not important (?)
• Mostly thinned CCDs
• In theory, CCDs can be delivered on time, but no time quoted; CCD vendor to still to be competitively selected
• Anticipated 500 million (?$?) for craft, CCD cost is significant fraction of this (?)
• Preflash of CCDs to preserve MTF versus radiation degradation
• 500 mW per CCD, 120 Watts for focal plane alone (without electronics); passive cooling

• Questions:
• Most cold comes through the epoxy, rather than the spacers
• Metal spacers determine epoxy thickness
• For non-flat CCD packages (such as SITe?), spacer also makes allowance for package curvature
• Epoxy is silver-bearing epoxy

• Roger Smith: review of CTIO/NOAO efforts:
• Good word for SITe CCDs;
• 13 microseconds per pixel => 50 seconds frame readout time
• 4.5-5 ms per line (parallel) transfer time
• radiative thermal coupler between cold source and focal plane; spring contacts would probably be fine
• less than 10 ms shutter transit time (pneumatic drive); tune with bleed valves; 1% accuracy for 1 second exposure
• must use master oscillator from one box (of the 4), must turn off oscillators in slave boxes to eliminate this noise source
• crosstalk from CCD to CCD is an issue not resolved sufficiently; as bad as 1 part in 5000; only one amplifier per CCD used
• problem with optical reflection off of narrow-band interference filters at band edges, solution is sol-gel on last surface of corrector optics
• full wells 70K to 100K e-, improvements discussed at future round table
• parallel clock drivers are DC opamp buffers, to analog switch, to LRC filter
• Packaging, buttability techniques:
• EEV quasi-4-side butting with connections under CCD
• From table to focal plane, 14 mm +/- 15 microns, factory adjusted
• Perched up on 3 spacers; is there adequate heat flow through spacers? Jim Beletic has measured 4 degrees C temperature difference from shims to center of CCD
• What is the tolerance allowable on the thermal gradient?
• Temperature gradients that are stable are OK;
• But, Gerry Luppino thinks 1 degree C variations in the time domain can effect (degrade) flat-fielding ability
• Cooling considerations:
• Some would want a smaller thermal mass and shorter cool-down time
• Doesn’t matter when everything works, but a long time constant hurts in the time domain when something breaks
• Perhaps a pre-cooling chamber and/or additional warm-up capability
• A thermal switch to alter the thermal time constant? Some IR cameras have such already.
• How are temperatures sensed? Once per array, once per CCD?
• Gerry Luppino has a single-point temp sensor, but uses a molybdinum definition plate (rather than aluminum or Invar) to get better better isothermal performance, he prayed and it worked; heater resistors are run in parallel and distributed, each with a cold strap
• Olaf Iwert uses a cold spring several centimeters in diameter; wants a temperature sensor ON the CCD, seconded by Roger Smith; the EEV CCD44-82 does have a temperature-sensor hole and uncommitted pins to which the sensor can be connected
• Roger Smith puts his pass transistor with his heater resistor both epoxied to the cold plate, runs in 3 wires, configured as a source follower
• Grouping of electrical signals:
• Grouping done by Olaf Iwert: can be done by FIERA given its current-sourcing capabilities
• With 2Kx4K in 2x4 array, parallel clocks are paralleled in 1x4 groups
• More careful selection of parallel voltages minimizes interactions?
• EEV parallel-phase-3 clocks must be clocked to a high voltage
• With caution such paralleling works for others
• Minimize number of wires going up to focal plane
• Serial clocks are also can be grouped, perhaps on the outside of the dewar
• Electrical connections to and thermal isolation of focal plane mosaics:
• John Geary thinks that the old ZIF sockets were unreliable; new ZIF parts from EEV seem more reliable, custom made to order, with new materials that take temperatue considerations into account
• Some use instead low-insertion-force (LIF) socket pins on a custom PC board, apparently OK
• Some worry that LIF sockets still put too much stress on the CCD pins
• Gerry Luppino is satisfied with Nanonics connectors, if they are not mechanically cycled much
• The SITe flex cable is not sufficient for thermal isolation, something else is needed
• But, the electrical shorting connector site is desirable
• Bruce Atwood puts on individual flying leads, maybe 4 minutes per wire, with no socket body
• Alternative devices?
• 4Kx4K:
• some need in a few cases for such a device, mostly 2Kx4K will do
• scientific device possibly to be offered (Paul Vu)
• there is a desire for such devices; a number of instruments could use this (for users upgrading from SITe 2Kx2K CCDs)
• Evolution of devices?
• EEV installation demo:
• Chip is held upside-down via a bridge piece; 3 screws
• Attach a guide pin to one of the holes
• Guide rod put through table, with CCDs looking down
• Guide rod screwed to back of the package
• Bridge is lifted out, box removed from underneath
• Unscrew remaining screws and remove bridge
• Lift and rotate until guide pins meet holes, complete lift
• Can’t damage an adjacent CCD given the height of guide pin and separation of guide pin to guide rod
• Install attach screws
• Remove guide rod
• Remove the guide pin
• Remove the shorting connector and make electrical connection
• About 0.2-mm gap between CCDs

• OTCCDs share (corners of) wafers with 2Kx4K imagers
• 2-micron lithography used on the CCDs
• Thinning toward 40-50 micron thickness
• To minimize fringing, want light internally reflected within CCD to exit the CCD rather than reflect back in
• 2-layer coating currently used: TiO₂ and Al₂O₃
• Question:
• Is fringing just from thickness of device, rather than from AR coatings? At longer wavelengths, no; but also might be from second cavity between gates and backing wafer
• First OTCCDs had pocket trap problems; triangular aluminum gate surface NOT smooth; final wafer anneal at 400C may be delaminating, lifting the Al; the lifted Al deepens the buried-channel potential, creating a pocket; 4-poly processing eliminates the majority of such pockets
• Questions:
• Flex circuit too soft to wire-bond to? No.
• Fringing: has computer simulation been done? Yes, by Don Groom.
• Blue response improvement? Will be addressed.
• Under aluminum, is there a barrier layer? Just straight Al, no tri-nitride(?) layer.
• Changes in leakage currents? CMOS-process leakage process too high, must change process; standard CCD process gives low enough leakage current.

• For CCD44-80, at 18KHz pixel rates, 2 e- read noise usually reached, with responsivity of 6.0uV/e- (10us + 10us slope time); typically 4.6uV/e- in the CCD42-80
• For CCD44-82:
• serial and parallel CTE typically 5-nines 8 (Fe⁵⁵ X-rays, -100C)
• About 1 e-/pixel/hour dark current at –100C
• Typically 260K e- full well, with test-data-sheet (nominal) voltages
• Absolute maximum peak-to-valley curvature typically 8 microns
• 6 extra tapped holes in the underside of the package, for general (arbitrary) use
• CCD30-11 CCD has been made with anti-fringing techniques, typically reduces fringing amplitude by x2 (as compared to CCD42-80); large-format CCDs being processed with this for study
• CCD65: 11MHz pixel rate, TV format
• CCD60, CCD65: < ~2 e- at max pixel frequency
• Questions:
• AR coating can reduce fringing; is this something else? Proprietary, but is a process at the FRONT side of the CCD; half of each pixel is thickness T, other half is thickness T + 75 nm
• At what temperature can cosmetic defects be frozen out? Limited influence; expectation of operation at –100C, optimum operating temperature –100C to –110C
• More detail of CCD60? 1-output, frame transfer. Availability? Early next year.
• Going slower on the very low noise CCDs? No point in going slower, but won’t help you.

• For X-ray grazing-incidence observing with spatial & energy resolution
• 100% pixel fill factor
• 60-70 msec frame time, 50-60 ns pixel time
• 1Kx1K format, but classically 1 mW per pixel, so need scheme with minimal power
• P-channel device; DEPMOS transistor, collecting electrons under the gate; 2K ohm to 10K ohm silicon
• The same can be made on a JFET technology, with shallow junction for the gate, with high-energetic Phosphorus implant under gate
• Had been on 4-inch wafers, going to 6-inch; amplifier per column, so 1K + 1K on-chip amplfiers
• Individual pixels have a hexagonal shape, 200x200 square microns; illumination from the back side
• Detector chip surrounded by 3 readout chips
• Read noise 20 e- at room temperature; hope that 5 e- will be realized colder
• Evaluating non-destructive readout to reduce read noise for low-energy (10 eV) photons
• Questions:
• Fill factor? Is 100% by design.
• Non-destructive readout transfer process? Might be done only in center of array; can be done for individual columns OR entire array.
• Pixel sizes? No plans to go lower than 22x22 microns.
• Transistor shaping time? Read speed can be increased, at expense of energy resolution.

• Large depletion depth gives nearly 100% QE from 700 – 1000 nm
• 12 detectors per wafer, left undiced to create 2x6 array
• Questions:
• What is the actual QE at 1 micron? 90% from simulation, and also measured.
• Is that internal QE? It is external QE. Silicon Oxide / Silicon Nitride AR coatings.
• Dark current generation? Has been cooled to –100C; don’t see dark current due to high read rate.
• What is CTE for these diode-gate structures? 99.99%
• What is the depletion voltage on backside? 100V – 200V.

• ITO is the backside transparent window/electrode that is biased
• Frame-transfer device being investigated
• X-ray Fe⁵⁵ CTE tests performed from the front side; from backside, charge repulsion has charge in a single pixel very seldom
• Variations in linearity less than 1%, done with optical ramp-up in scan mode
• Temperature-related QE effects should not show for wavelengths short of 900 nm
• With 12 usec dwell times in DCS integrator, 4-7 e- read noise
• Less-that-perfect polishing of back surface shows as 2/3% QE variation
• 2Kx4K 15-micron device in process, next 6 months or so to first realization
• Questions:
• Tell about cosmic rays? Don Groom will show.
• Dark current uniformity? Have never seen hot spots from bulk; has a guard ring around the dark side
• Residual image? Can have, but can erase with proper parallel clocking.
• CCDs with flatter QE in the U-band? LBNL tests don’t go below 380 nm. ITO starts to become opaque at these short wavelengths. ITO is 450 Angstroms, over quartz, determined by AR coating needs.

• Backside bias voltage can control "how fuzzy" the images are.
• In a thinned back-illuminated CCD, the field-free region dominates the PSF
• Tailing is real, non-Gaussian distribution, but has same FWHM as the Gaussian distribution
• Questions:
• Anything worse with higher volts? For the most part, no, but some residual image effects.
• Dark current? Pretty much constant as a function of backside voltage.
• Cosmic ray distribution? Isotropic above Van Allen belts, non-uniform distribution on the ground
• Packaging for 4-side buttability? Can’t get devices as close, constrained by the bias voltage (which needs to be two wafer-thicknesses away from the dicing saw cut)

• Will have a notch channel
• Thinning ala Lesser, perhaps with a CatC process (thin copper coating that reacts with oxygen)
• One device per 5-inch wafer (with other devices filling the wafer periphery); Milpitas fab upgraded to 5-inch recently
• CCD447 will be the Triana mission sensor, flying in November 2000; catalog item
• CCD486 is bump-bonded to AlN substrate for backside illumination; will be a catalog item; delivery is still a question
• Will transfer Lesser’s thinning process from U of A to LMFS
• Questions:
• 2Kx4K format? A 2Kx4K is possible but not yet planned.
• Impending sale of Fairchild from Lockheed Martin? Hopefully makes no change.

• Questions:
• What can Dick do? US$150K-200K per lot run on undiced wafers, unthinned.

• Aluminum bussing (a change from at present) for higher-speed clocking
• 200K-250K e- full well for 12-micron pixels
• Developing backside CatC (Chemisorption) coating with Mike Lesser
• 600 ns row-shift time operating now
• Questions:
• SITe does have (split) frame transfer with masking in back illuminated format.

• Mix of 5 laser dyes to convert from UV to silicon’s peak absorbtion; not much used in this day and age
• Rapid spin coating of the thick CCDs, no problems with bond wires (up to 2500 rpm, things DO start coming apart at 3000 rpm)
• Crosstalk:
• 1 part in 10^4, in layout of the Leach controller, possibly in the ground planes; CCD load resistors stayed in place, only signal path disconnected so current still through both on-chip amplifiers
• In the CCD, crosstalk not more than ½ electron
• Current plan is to individually thermally regulate each CCD in an array
• Need to use indium between ceramic package and copper cold block? Suspected indium is not necessary

• Mingshe Wei: parallel clock voltages:
• Amplitude too high, get spurious charge injection; too low, get residual image
• Do high-amplitude erase to get rid of residual image, then low-amplitude erase to get rid of spurious charge from the first erase; the positive clock voltage is probably critical
• Using trapezoidal clocks minimizes spurious charge injection while minimizing clock time
• Fred Harris: trapezoidal clocks were only modifier to (slightly, 5%) improve SITe 2Kx4K full well
• Bruce Atwood: why does the clock-drive wave shape make a difference?
• Roger Smith: why does the positive vertical clock level influence spurious charge? Turning down the volts makes a difference, but why?
• Gerry Luppino: tri-level clocking?
• Ralf Kohley : tri-level clocking DOES work.
• Roger Smith: spurious charge seems to occur on a per-transfer (per line) basis.
• Gerry Luppino: can tri-level clock with analog switches, just costs you more switches.
• Roger Smith: bi-level clocking, but changeable voltage rails depending on clocking mode.
• Barry Burke: thinks this spurious charge injection comes from the potential difference from the channel to the channel stop; might be fixable via changed CCD manufacturing techniques
• With EEV CCDs, spurious charge mostly not seen for clock swings up to 15V
• Roger Smith: in some cases, last row next to serial register did not have as large a full-well capacity, and any relaxation of the parallel-clock voltages changed the well depth versus time; found on any of 3 2Kx4K SITe CCDs lacking transfer gates, when readout was performed in MPP mode (rather than integrating in MPP and readout in non-MPP); not AC-coupled preamp, so not a coupling issue
• QE measurements:
• A call for a standard (a standard CCD?)
• What accuracy can you get, and what is the dominant source of error?
• What about the geometric factor for the spacing of the CCD from the integrating sphere?
• At ESO, CCDs are in the same place (or try to).
• Gerry Luppino: QE measurements ARE repeatable; photodiodes DO fade
• Rich Stover: photodiodes DO fade from 900 nm longwards with time; don’t trust your photodiodes more than 2 years old. CCDs tested for QE in photodiode mode?
• Jim Beletic: do we believe QE measurements better than 10% accuracy?
• Don Groom: can cross check the whole process by checking the reflectivity; sanity check using a dichroic mirror. Taking ratios of ratios, not making "absolute" measurements at any given time, is extremely stable: fiber split source light to object AND a diode, then to diode and a diode, then take ratio of ratios?
• MOST test QE in CCD readout mode; a few use purely photodiode mode (without clocking the CCD); Philips does clock the CCD but look at the reset-drain current, illuminating the whole CCD, eliminating the gain of the output amplifier
• 3 groups have measured CCD surface reflectivity, but not always for a QE measurement; you don’t operate the CCD, don’t cool the CCD, so no window in the path; don’t make such a test shortward of 420 nm.
• How many groups recalibrate their reference detector’s QE measurement after time? Some buy a new diode; some continue to use the same photodiode without recalibration; Philips and SITe do pay for recalibrating the same photodiode on a regular basis.
• Optimizing CCDs:
• Voltages determined at the test bench, then same voltages used when put into the array, but voltages not retested after installation into the array; voltage-grouping needed for clock-paralleling
• Scientists should test/verify the numbers from the manufactures (not just QE)
• Some projects need long-term stability, more so than knowing the absolute value of the measurement; repeatability is more important for COROT space mission
• PSF testing:
• Don Groom calls for such testing
• Philips group does such testing
• CCD-world:
• Please present the solutions, don’t only pose the problems
• If you are reading this on CCD-world and Fred Harris got it wrong, PLEASE submit a correction to CCD-world!!!

• Artificial stars projected into the mission optical paths (to establish fiducials)
• Investigating CCD limitations for centroid accuracies < 1/100 of a pixel
• Test images diameters ~7 pixels
• Test frames taken in stare mode with Kodak KAF1600 CCD with 9-micron pixels
• 1/300 of pixel is possible
• Questions:
• Were spot illuminations moved to account for the frontside gate structure? Not within a test series, but may have been varied between test series.
• Are different test results expected with CCDs in scan mode? Not yet known.
• Will GAIA fly thinned back-iluminated CCDs? It is hoped, for QE sake, but not yet determined.
• Intrapixel sensitivity variations? Not tested with these tests.

• Illuminating a small (rectangular) part of a larger (2D) CCD, then move charge in time (CCD in scan mode without the image motion that would make this TDI); works for bright objects
• Or: use half of the chip as above; when chip area is filled and an integer number of periods has been reached, then move the charge image back to the starting position and continue integrating; go for perhaps 50 repeat cycles to improve the final signal-to-noise
• Can also be used for eclipses of binary systems
• Questions:
• Have phase-resolved spectra been done before/elsewhere from the ground? Apparently no.
• What timing accuracy is needed for the resynchronizing: 25 ns is what they have (with FIERA), and is sufficient for a pulsar with a 33 millisecond period
• What is the spectrographic resolution needed? 1000?
• What is the slit width? 4 lines (pixels).

• Sun-synchronous orbit => 3 Gbytes/day
• Analog Devices AD9802 used for signal chains; ? space qualified ?
• Questions:
• What is the stability of the gated image intensifier? Not yet known.
• Happy with the AD9802? Not yet known; hope to comments on CCD world when found.

• Comparing images before AND after focus, nearly simultaneously (quicker than the scintillation) using the same detector to cancel out common CCD and instrument influences
• Use a membrane mirror oscillating at about 2500 Hz to get to both sides of focus with a common optical path and common CCD detector
• Questions:
• (not recorded)

• Power supplies are at present linears; will try switchers
• Sequencer is RAM based, 24-bits wide; 50MHz clock to address generator, with external synchronization option
• High-speed shunt prior to clamp-and-sample CDS stage allows faster settling of the signal chain immediately after the reset pulse, then shunt is removed to re-establish the normal signal chain path
• ADC is 10MHz, 12-bits
• Improvement from 1-arc-second seeing to 0.2-arc-second seeing with 40-arc-minute field
• Questions:
• In video processing chain, 4 filter bandwidths; what time constants? Gains and time constants are set by resistor selections; particular values not on hand.

• Must deal with 72 channels of science CCD output; system will max out at 80 channels
• Maybe 4 cryotiger (?) units possibly instead of 2 dewars with 50 liters of LN₂ capacity, to minimize flexure
• Sequencer defaults to PROMs, can changeover to RAMs, so camera comes up with no computer; timing PALs for (subpixel?) timing loaded from PROMs
• 14 of HI201HS-based clock drivers per CCD with BUF634 output drivers after switches, quad DACs for voltages
• ADS937 ADC (1MHz) with dual-slope-inegrator CDS with HI201HS switches; good differential nonlinearity
• LTC1604 ADC tested; has its own internal sample-and-hold; differential nonlinearity problems associated with the change of the LSB of the upper byte (every 256 ADUs), true for all 4 parts tested; putting an external sample-and-hold did not improve this problem; not thought to be a board layout problem
• "All analog designs require lots of capacitors."
• 8-layer board has 2 layers of power planes and a ground plane; power layers used to shield data bus lines; 5 wiring layers; in each of the 4 channels the power planes are separated (for isolation) by channel; DC into boards is +/-8VDC, +/-18VDC; ACQT technology bus drivers (QT for quiet)
• On ADC boards, one DIN96 connector for video inputs only, digital on other DIN96; on driver boards, analog outputs on one DIN96 and again digital on the other DIN96
• Questions:
• Signal chain opamps? Linear Technology 1356-1362 series
• Clock driver circuitry? Of traditional design, switches with unity-gain buffers.
• Power dissipation and heating? Possibly liquid-air heat exchangers.

• Started out with decision to go with PCI card; but switched to starting with the SBUS card
• Prontor, Compur and pneumatic shutters need controlling
• ID-connector on dewar to identify dewar to electronics box
• Timing card abort-read-out feature added
• EEV13 giving 3.3 e- read noise with 2 + 2 microsecond CDS integrator-on time
• Windowing (region of interest) not yet implemented per ING specification (although other groups have implemented windowing but not to ING’s needs)
• Questions:
• Power in the beam? SDSU box dumping about 50 watts, no shroud.
• Upgrades? Haven’t changed (mostly) any boards, other than remoting the shutter control away from the utility board, and a change for preflash; piggy-back board added to utility board.
• Comment: Mods to SDSU boards are encouraged, opamps can be swapped, capacitors changed.
• Comment: No longer called SDSU.

• 400K pxiels/sec, with ADS-937 ADC
• Fiber optics link board piggy-backs onto PCI board

• John Geary: DG611 series analog switches: 21V supplies max
• Fred Harris: Lockheed Martin extremely happy with these parts as clock drivers in space applications; no latch-up, rad-hard for off-the-shelf parts; will clock at 40MHz; HI201HS will NOT operate with a 40MHz input clock; the DG611 series should switch to the negative rail, but cannot go closer than a few (?5?) volts of the most positive rail.
• John Geary: DG611 series has less charge injection than the HI201HS.
• Clock driver buffers:
• LM6321 eats 15mA quiescent but puts out 1A.
• BUF634 has tunable quiescent current with a single programming resistor and puts out 300mA.
• Some of us still just using the analog switch output unbuffered.
• DC restoration on preamp inputs: AC-coupling cap either teflon (Bruce Atwood) with no DC restoration, or Panasonic polypropylene (John Geary) with DC restoration.
• Roger Smith still advocates DC-coupled preamps, die hard; downside: more complicated, must subtract off a voltage, so need much higher voltage supplies on the preamp opamp and they will get hot, need to adjust the DC offset voltage as a function of an varying DC bias voltages.
• Bruce Atwood: MUST test dual-slope integrator implementation very carefully.
• Bright-edge overscan test: big flat field, look at transition to the overscan region; possible to do a 65535 ADU flat field and see ½ ADU bump in the first overscan pixel.
• CDS: integrators versus clamp&sample:
• For white noise, dual-slope integrator is ideal solution.
• Put the input analog switches at the virtual-ground node, not prior to the input resistor.
• Clamp&sample is a crude integrator done with an RC filter.
• Time jitter for fast dual-slope integrator schemes contributes noise. No jitter problem seen for integrator on-times of 1 microsecond or greater.
• Why not create an entirely DC-coupled system, taking two ADC conversions per pixel?
• In any CDS system, some bandwidth limiting must take place; why not do it at the integrator?
• ESO started with clamp&sample, for time-domain verstility, and still like it; even if dual-slope is 20% quieter (?) than clamp&sample, the CCD noise still dominates (?).
• John Geary puts two reset switches across his integration capacitor, source-to-drain and drain-to-source, for more symmetrical reset.
• Roger Smith claims that double pulsing the integrator reset switch does nothing if the dielectric absortion time constant has not been reached, or the integrator capacitor will still be relaxing after the last reset pulse.
• The analog tapped-delay-line CDS architecture seems not to be in use by any conference participants.
• ADCs:
• We want the CS5101A but running 10 times faster.
• ADS-937 will burn your fingers.
• Is the (new) MAX1200 from Maxim a viable new ADC that runs fast and cool? Bruce Atwood has a delivered demo board.
• LTC1604 may in fact be a viable part, with a current-feedback opamp (Analog Devices?) driving the input, and perhaps a multilayer board is a necessity.
• Barry Burke is doing feedback on the on-chip amplifier for improved linearity over the entire dynamic range, given the larger microvolts/electron being delivered to the amplifier; details not available at present.
• 18-bit analog systems:
• Data systems don’t like it, but in the analog domain 18-bits can be done (John Geary) or should be done (Jim Beletic).
• Bruce Atwood has systems for either CCD or IR, so co-adding capability already there; so output formats of 1 or 2 or 4 or 8-bytes width already built.
• Square-rooters and nonlinear transfer functions:
• Nobody working on it;
• What about 18-bit ADC with a digital lookup scheme to offer a square-root (or other nonlinear) transfer function? Then data path is still not more than 16-bits wide.
• Do you have to do the offset and gain BEFORE the nonlinear transfer function?
• Comment: most optical systems do NOT have 16-bits of scattered-light optical dynamic range
• Switchable gains:
• Roger Smith: offer it to the observer, as something to be set and left (not dynamically changing on a sub-frame basis?).
• Gerry Luppino: do NOT offer switchable gain, so as to not undersample the noise when the gain is turned down.
• Power supplies:
• Preben Norregaard: tried switchers, couldn’t get the interference noise down to linear supply performance.
• Ray Du Varney: will try phase-locking all switchers to a common clock.
• Roger Smith: has used switchers with good results, with FFT analysis the switchers are contributing 1% of the total noise (for a particular sample rate); but as one goes to faster pixel rates, the increased bandwidth may make the switcher transients show up. He is also concerned with clocks for fiber optics links versus transputer clocks versus ADC clocks.
• Bruce Atwood: doesn’t use them, but switchers keep the AC mains frequency out of the system. Wishes for a 10MHz switching frequency.
• Roger Smith: transformer radiations much improved if using a 400Hz mains frequency.
• Flex PC circuits:
• Gerry Luppino: 4-layer flex board with ground plane at the hermetic connectors (but not up to the CCD?), to route signals to the CCDs and provide thermal isolation. Learned a lot from the MIT/LL people.
• Kapton/polyimide substrates
• No ground planes
• All epoxy & polyimide construction (NO acrylic adhesives); MUST be specified to the manufacturer
• Avoid cold thru-hole vias
• Can wirebond to such flex circuits
• Can wrap them around a bend radius as small as 1mm
• ESO doing since 1991, space qualified, no delamination problems: Company Bauman (?) in Muenchen can do this; ESA has a specification; can do as many layers as you want on the rigid portion, must limit number of layers to maintain flexibility.
• Don’t bend the flex portion during construction, wait until the very last, to give best reliability (and is required for space applications)
• Hermetic connectors:
• MS38999 round hermetic connectors used by Gerry Luppino; 2 CCDs/connector
• Why not eliminate the hermetic connector and route the flex PC potted through a feedthrough? Barry Starr will be trying this. Check out "Pave Technology" web page. There are vendors ready to do this.
• Ray Du Varney: used D-type feedthrus; it is the touching of the pins that breaks the vacuum seals; so wires are soldered to D-type hermetic pins, then the mateable D-type connector is an inch or so away, so the mechanical stresses are never transferred to the metal/glass seals.
• Decoupling the cold link to the focal plane:
• Should the cold be delivered in the wiring path, via a cold clamp? Roger Smith has done this once; worry about thermal contraction effects.
• Signal chain tests and stimulators:
• Bruce Atwood: programmed generator with stepped levels fed into signal-chain input, going through the full dymanic range in a single frame. Fast high-quality DAC initially; now a crumbier DAC combined with an analog switch to change levels in a quality manner.
• Barry Starr: need for (more rigorous) signal change specs, such as pixel-to-pixel crosstalk, MTF, signal-chain linearity (independent of CCD linearity)
• Call for a poster for the next meeting, characterizing their test generator and the results derived.
• Roger Smith: how about a 4:1 mux with inputs reset-feedthrough (nominally fixed), signal (DAC generated for changing data), reference (nominally fixed), and ground
• Fiber optics links:
• HDMP1022 and HDMP1024: parallel 32 bits TTL to serial, 1.2Gbaud serial link, uses multimode fiber
• Perhaps 20 different CCD controller implementations represented within this meeting’s participants.

• What contaminants?
• Water, oil, vacuum grease, oil droplets, plasticizer from wire insulations