Sharing of bias phases

[roger smith x294]

Reply to .....

> To: ccd-world at ocar01.obs-azur.fr, ccd_plumbers-l at ocar01.obs-azur.fr
> Subject: Sharing of bias phases
> Date: Mon, 16 Oct 1995 10:43:48 +0100
> From: Olaf Iwert <oiwert at eso.org>
>
> I would like to call upon some comments for the following points :
> 
> Most CCD controllers do NOT provide for the possibility to supply each bias 
> gate (e.g. of a Tektronix 2K CCD) with an independent bias voltage.
> 
> As we know, some voltages especially on those devices do require individual 
> optimisation of their voltage (e.g. Last Gate per dedicated output),
>  my question is whether someone sees from the design and semiconductor 
> physics point of view any problems to drive the VRD voltages with individual 
> voltage ?
> The same question for VDD ?
> The same question for VLG ?
> 
> To already prevent some answers I'd like to add that we have done so with
> mostly good success (as probably most of you), however my question is more 
> whether it is against the theory to do so : 
> VRDA and VRDB are the end points of the same serial register.
> In case of simultaneous clocking/resetting through/of output A and B a 
> potential gradient across the register channel exists which leads to a small 
> cross current in case of different biasing for VRDA and VRDB ?
> 
> Furthermore I'd be interested to know whether there are observations from the
> experimental or theoretical point of view to opt for certain preferred output
> combinations in case one combines the voltages of specific output related bias
> gates.
> 
> E.g: On a TEK2K device : 
> 	Which combination is better ?
> 
> Bias 1 :VDDA, VDDB
> Bias 2 :VDDC, VDDD
> 
> OR 
> 
> Bias 1: VDDA, VDDD
> Bias 2: VDDB, VDDC
> 
> OR any other combination ?
> 
> The same question for combinations of VDRx ?
> The same question for VLGx ?
> 
> 
> I'm interested in ALL comments for all possible CCD types, however do look 
> forward specifically to comments on TEK2K devices and their users.
> 
> 
> 
> ===============================================================================
>   Olaf Iwert                        E-mail :               oiwert at eso.org  
>   European Southern Observatory     Phone & Voice Mail :   +49-89-320-06-353  
>   Optical Detector Lab              FAX :                  +49-89-320-23-62
>   Karl-Schwarzschild-Str 2
>   85748 Garching
>   GERMANY                         
> ===============================================================================



Olaf and everyone,

We use fully independent bias voltages for each amplifier in the
Arcons.  Most of our experience is with Tek/SITe quad readout devices
(1K, 2K square) and Lorals with 2 outputs.

I was grateful for John Geary pointing out to me about a year ago that
we might be driving a current through the channel due to VRD
differences, since VRD is connected to the channel during reset. This
left me puzzled that we do not actually see any effect which can be
clearly attributed to VRD differences.  I didn't see any change in
performance when I connected all VRD's together in one system as an
experiment.  So I was interested to read David Burt's explanation which
was relayed by Paul Jorden:  (thanks Paul)

> In general one could assume that outputs are independent, and should
> operate with different voltages perfectly well. This is especially true
> of relatively unsophisticated designs. Usually RD & OD are
> reverse-biased with respect to the substrate, and so current cannot
> flow between different outputs easily.

We have found that having independent voltages is a plus for optimizing
linearity and to a lesser extent noise.  Although the differences in
optimum voltages is usually small for Tek CCDs, we think it is worth 
having the option for the independent adjustment capability on
VDD, VLG and VDD.  Even if you don't end up with different settings it is 
very nice to be able to compare the amplifier you are adjusting with one 
which remains untouched.

The other thing to consider is crosstalk, primarily for VDD, as we discussed 
in a recent mailstorm.

If I was connecting biases in common, I would start by connecting a-b
and c-d on the Teks so that the one serial register is driven by the
same voltages.

Are you interested in our clocks setup too?   Each clock pin on the CCD
has a separate analog switch so that timing is independent, but some
levels are connected to common voltage buffers.  We drive all RG's from
the same pair of levels.  Recently I have taken to running SW from the
serial levels.  I split the serials into left/right where possible to
reduce the capacitive load on a given driver, but usually run them at
the same levels.  I could use this to adjust SW's independently if need
be, since the other serial levels are not that critical.

We have buffers fpr each level for each parallel phase and TG for each
half of the chip... 16 in total.  Again, this reduces the loading on a
given driver and allows for one to play around with improving
cosmetics, charge injection and full well, and dark current, if you can
devise a way of navigating the parameter space efficiently!

Roger

Senior Electronics Engineer / Manager - Array Controller Projects
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