optimizing parallel clock voltages

[Ralf Kohley]

Hi Roger,

I don't have a detailed procedure for setting the parallel voltages, but
I would like to give some remarks about our experience with Loral 2k's.

I found out that you can determine the inversion voltages (low voltages)
of a MPP-CCD by using a point-like source. The source should cover
a few pixel and reach the full well capacity of the MPP-mode in its maximum.
You begin with setting all three phases to garanteed inversion, say -8 V.
Expose the CCD with the point-source and read it out normally to get
the normal profile of your source.
Then, in the next step, you pick out the phase with the additional boron
implant, say P3, and after exposing and closing the shutter, you increase the
voltage of P3 for a short time, say 0.1 seconds, and immediately go back
to -8 V and read out the CCD normally afterwards.
If you do it successively with increasing voltages for P3 (I did it in
steps of 0.5 V) you see that at a certain voltage for P3 the profile starts
to bloom. That's the point where you drive the boron doped phase out of
inversion (in my case it was at -4.5 V).
At another voltage you see that the whole charge has bloomed. That's
the point where the barrier (P3) and integrating (P1 & P2) potentials
become equal (around -2 V in my case) for 0.1 seconds. The difference (2.5 V)
between these points roughly describes the intrinsic potential difference
between the normal phases and the additionally boron doped phase.
If you use (-8 V, -8 V, -2 V) as your integrating voltages and increase
P1 and P2 after exposure, they become integrating potentials again after
leaving inversion, which you will see in the image as the reappearing
of a profile.

So far for setting the low voltages.

For setting the high voltages we changed the high voltages step by step
and measured the minimum of surface and bloomed full well, one time
using the same high voltage for all phases and another time driving
P3 with an offset of 2.5 V. The maximum of the full well curves describes
the optimum high voltage for the phases.

I wrote a paper about the handling of our Loral chips for the last SPIE
conference at Photonics West. You can read the paper at my WWW page,
if you like (it's still under construction):

Point at:
    http://aibn55.astro.uni-bonn.de:8000/~rkohley/paper/paper.html

I hope that my remarks might be helpful for you and I would be very
interested to get a recipe for setting up a CCD, if you'll find out
a detailed procedure.

-Ralf

rkohley at astro.uni-bonn.de