Parallel clock adjustment procedures?

[roger smith x294]

Fellow CCD pundits:

I would like to draw on your experiences in optimizing parallel clock
voltages.  I have encountered descriptions of the relevant effects but I have
never seen a complete discussion of the best methods to measure them.

I would like to hear of a systematic procedure for optimizing the clock
levels.  Do you have your own written procedures, or references to published
ones?

I get the impression that a common method is to choose the recommended values
(say +3, -8V) then adjust these a bit to see what happens.  I don't find this 
very satisfactory, especially given that there are two levels on each of
	- transfer gate,
	- the barrier phase (for CCDs with MPP implant), and
	- the non-barrier phases,

I'll try to stimulate some discussion by summarizing my understanding of the
issues.  Please correct any misconceptions...

GOALS
-----
Minimize dark current.
Minimise spurious charge generation.
Minimize cosmetic defects, hot pixels etc.
Ensure good Charge Transfer Efficiancy at all signal levels.
Maximize well capacity.


SETTING LOW VOLTAGES
--------------------
Aim:	Make them just negative enough to ensure that the surface is populated
	with holes which will recombine with dark current, and remnant image
	electrons.  This also creates the greatest possible barrier between
	lines helping to maximize full well. 

Too high -> not inverted, full well, dark current & remnant image deteriorate.
Too low  -> spurious charge generation increases (?) due to greater number
	of holes being driven back into channel stops by high going edges,
	and the greater dV/dt implied on rising clock edges.

Typical values:
	P1 & P2	= -7V to -8V
	P3 offset "a few volts" relative to non-barrier phases in MPP CCDs ?
		(How big should this offset be?)
	  	or same as P1 and P2 for CCDs without Boron implant.


SETTING HIGH VOLTAGES 
---------------------
Aim:	To maximise well capacity while minimizing spurious charge injection.

Too high -> Charge interacts with traps at surface before blooming. This
	causes trailing of bright pixels vertically (or even horizontally in
	MPP CCDs lacking implant under TG -- see my recent messages).

	-> Spurious charge injection increases due to the faster slew rate of
	the rising edge (that drives the holes back into the channel stops
	increasing the probablity of creating an electron-hole pair). 

Too low -> Loss of well capacity (blooming occurs at lower signal levels).

Typical values:
	P1 & P2 = +1V to +3V
	P3	= +3V to +5V for CCDs with MPP implant ?
			  or same as P1 & P2 for CCDs with no implant.
 

WHAT ARE THE EASIEST & MOST SENSITIVE METHODS TO MEASURE...

 o Effects of charge reaching surface ?
	...Y-overscan edge response for bright flat fields?
	...departure of variance curve from linear?
	...look for bias level shift when heavily saturating a
		localized spot, using MPP mode. (See the problem
		reported in my recent messages)  Only usable
		for quad readout CCDs since one clocking direction
		will probably not show this behavior.

 o Full well ?
	...blooming of high contrast target image ?
	...saturated images using anti-blooming clocking ? (cf:Janesick)

 o Spurious charge injection ?
	...X-overscan edge response for zero length darks ?

 o Onset of inversion ?
	...dark current at elevated temperature ?
	...measure full well using anti-blooming clocking ?

 o How to set P3 relative P1/2 ?
	...repeat all of above ?  Tedious!!


WHAT ORDER OF ATTACK ?
 o Low levels first, then high?
 o P1/P2 then P3?  ...then iterate?

-------
Incidentally, we have found it necessary to reduce parallel clock high levels
for Echelle spectroscopy compared to the settings used for imaging, in order
to reduce spurious charge injection in photon starved applications at the
expense of (unneeded) well capacity.  We pretty much always have enough
spurious charge to impact noise performance on our Tek CCDs if we optimize for
full well, in spite of running the clock edges very slowly.  I wonder if there
is any combination of clock levels which will allow a single set of voltages
for all applications?

By the way, splitting the image (reading through both serial registers) halves
the spurious charge since the number of parallel transfers is halved.
------

What methods do you use?... 

Roger,     rsmith at noao.edu