serial "smearing" explained

[roger smith x294]

Fellow CCD pundits,

Here is one plausible explanation for the puzzle I described in my last
message, ie. a bias level shift which was seen on lines containing saturated
stars.


THE SYMPTOMS:

	o Tek2K operated in MPP mode; near perfect silicon with very good CTE

	o Bias level increases as bloomed stars pass through the
	  serial register.  The effect occurs both before and after
	  the saturated pixels, and in the overscan area.

	o All other behavior was excellent;  controller working well.


THE CURE:

	o Reduce P3-high from 7V to 5V.


EXPLANATION:

With such a high P3-high voltage, charge was reaching the surface traps as it
passed over the last P3 electrode.  This CCD (like most CCDs) has a design
defect in that Tranfer Gate corresponds to P3 but is not located on
ploysilicon layer 3 (the last to be laid down) and thus does not receive the
Boron implant.   So in MPP the line next to the serial register is unconfined
during serial readout.  We use fancy clocking to move the charge out of this
last line, effectively making the CCD one line smaller.

So the problem is that charge trapped in surface states at the last P3
electrode evidently is released for a long period (greater than the time to
read the entire line).  With no TG implant to confine it, it simply falls
into the serial register where it contaminates every pixel.

Reducing P3_high simply ensures that charge spills out of P3 before reaching
surface traps.   To verify this theory we tried running at the high voltage in
non-MPP mode and as anticipated the bias shift disappeared since the charge
released from traps now falls into a well under P1 or P2 in the last line.

An interesting feature was that the bias shift only occurred in one clocking
direction.  A plausible explanation is that the P1 and P2 potentials when
inverted are slightly different and this form a "down hill" series of
potential steps to the serial register in one direction but create a small
structural pocket in the other direction.

I have one misgiving with this explanation.  Why is it that charge released
from the P3 surface traps does not recombine with the holes populating the
surface since this is what MPP mode is supposed to do in order to suppress
dark current?  Maybe I have not successfully inverted P3.

------------

I hope you found this interesting.  Your comments would be very welcome.  Are
there an other explanations?  I am sure that between us we have a lot of other
"learning experiences" we could benefit from sharing.

Since admitting to ignorance is the first step in learning, I will send
another message asking about procedures for setting parallel clock levels.

Roger

rsmith at noao.edu