Fast erase & line skips.

[roger smith x294]

Tim Hardy wrote to ccd-world........

Has anyone successfully operated a CCD in a parallel flushing mode where the
serial gates are all held high while the parallel clocks are runnning instead
of periodically flushing out the serial register?  The theory is that the
charge should all drain out to the output node, but I have been trying it
with a Tektronix TK512 and have had no luck - I always get overflow from
the serial register into the imaging area.

Are there any tricks to it?

________________________________________________________________________

 Tim Hardy
 Dominion Astrophysical Observatory           E-mail: hardy at dao.nrc.ca
 National Research Council Canada             Phone:  (250) 363-0015
 5071 W. Saanich Road                         FAX:    (250) 363-0045
 Victoria, B.C.   V8X 4M6
________________________________________________________________________

                                                                         

Tim,

This is my standard method for erasing the CCD and for skipping
lines between Regions of Interest.  I take all the serials and Summing
Well high (5V), and Reset Gate high so that the the charge will drain out
the Reset Drain, while clocking the parallels.  Before using the serial
register again, which is to say between line skips/erase and start of
region/readout, I clock all the pixels plus overscan out of the
serial register, which fills up to the level of the barrier formed by
the Last Gate.  ie: you need to use negative clocks to lift the
charge over the Last Gate onto the output node.

With some CCDs I get one bright line at the start of the image or
region of interest.  I hypothesize that this is due to clock in charge
into the serial register faster than it drains out through the
serial register.  It is no longer being pushed along by the clock
potentials but by self-repulsion of the charge.  Anyway, whatever the
mechanism, I consider it a good trade.  You must discard one line
at most in exchange for much faster erasing and regions of interest.

It does work, so what could be going wrong?  I suggest that you check
that Last Gate is not too negative.  A minimum requirement is that
LG be more positive than the low level of the last parallel clock
(usually Tranfer Gate), but maybe to "ease the flow" you need it
even more positive.  (I'm guessing here, since I've never had
cause to worry about it.)

The other thing to watch out for is that your positive parallel clock
levels are not too high.  You don't want charge to get stuck in the
surface traps when the charge backs up since this can take many line
times to be relased and will be deposited in the first lines of
your Region of Interest.  It is less of a problem for readout which
usually occurs well after the erase.  Anyway, surface full well is
bad because saturated stars bleed this way too.  You want the charge
to bloom before reaching the surface.         


Check you parallel clock voltages.  This mode runs your clocks faster
than you have been doing and the increased current drawn by the CCD
plus slope control filter capacitances could be overloading your 
clock drivers.


Please let us know how it goes, even if it was a simple error since
it's always useful to know what to avoid doing.

Roger Smith,  CTIO

rsmith at noao.edu   ....Use this address only since I'm changing computers.