Parallel clock rise times

[roger smith x294]

Jim (Beletic),

The spurious charge figures I quoted were for a Tek2K under normal
readout/erase conditions and not anti-blooming clocking.  On Dec 4, I
described how the amount of spurious charge generated was a strong
function of P3_high.  The rise and fall times were controlled by an LRC
filter placed between analog switches and the CCD.

	tau	= ~10 us
	C_CCD	= 40 nF/phase   (each phase driven separately)
	C_filt	= 210 nF
	L_filt	= 500 uH
	R_filt	= 72 ohm	(includes inductor coil resistance)
	R-Sw	= 20-40 ohm

The inductor provides faster settling for a given maximum slope and
ensures that the slope control filter attenuates interference
aggressively at high frequencies.  The capacitor is made very large
relative to the CCD phase-to-phase capacitance to control clock
crosstalk.  Maxinum parallel clock period is about 150 us with this
setup, but in practice we extend parallel clocks to about 1 ms.

Roger Smith, CTIO