From apo at tightfit.demon.co.uk Fri Dec 12 20:24:10 1997 From: apo at tightfit.demon.co.uk (Cyber Rover) Date: Thu Jul 29 11:54:22 2004 Subject: The Knell of Parting Day Message-ID: <3491FFDA.3CEB@tightfit.demon.co.uk> Posted to CCD-world: -+-+-+- Message to the CCD World E-mail Exploder... -------------------------------------------- Hi Folks - to keep you up-to-date The UK PPARC announced today the rejection of the RGO business plan and hence the viability of the RGO as we now know it. The result of this is that the organisation as it now is will cease to exist in the first months of next year with an attendant loss of key staff and work... This is VERY BAD news and it looks certain the 350 odd year old history of the RGO is at an end. Some pieces will be picked up next week and there have been further options suggested all of which sound tenuous at the very least... I am sorry this is such bad news before Xmas but that appears to be how the system opperates here.. All the best for Christmas PAddy -- ___________________ * _-_ \==============_=_/ ____.---'---`---.____ * \_ \ \----._________.----/ * \ \ / / `-_-' * * __,--`.`-'..'-_ /____ || * `--.____,-' ...to boldly go where no one has gone before! REFORM:: 'To train, develop or mould by instruction, discipline or example...' Captain Paddy... -- -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From conroy at mso.anu.edu.au Fri Dec 12 10:02:42 1997 From: conroy at mso.anu.edu.au (Peter Conroy) Date: Thu Jul 29 11:54:23 2004 Subject: Apogee Message-ID: <3.0.1.32.19971212090242.0090b530@mso.anu.edu.au> Posted to CCD-world: -+-+-+- Dear Colleagues. At Mt Stromlo we are considering using an Apogee CCD camera system fitted with a Hammamatsu thinned 512x250 pixel CCD for a spectrograph guide camera. Is there anyone out there in the CCD world with any any experence with Apogee controllers or Hammamatsu thinned chips? If so could we please make contact with you? Regards -------------------------------------------------------------------- Peter Conroy - Senior Draftsman - Design Office Mt Stromlo Observatory - Canberra Australia Private Bag Weston Creek PO ACT 2611 Australia Email - conroy@mso.anu.edu.au Phone - 61 02 6279 8022 Fax - 61 02 6249 0233 -------------------------------------------------------------------- -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From MYPIXEL at aol.com Wed Dec 3 11:44:08 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:23 2004 Subject: Thinned Speed Message-ID: <971203104340_1706556673@mrin39> Posted to CCD-world: -+-+-+- Gary . . . that (below) is really something .. Pluto after a few CCD Wor= ld e-mails got real slow. Any chance we could talk about thinned speed CCD physics or are these discussions in the paper you have referenced? I'm mo= st interested in getting holes in and out of a CCD without a substrate. Is t= he device you have (below) three-phase? Unsymmetric clocking (such as 3-phas= e) makes hole transfer inefficient. What is your line transfer time at full well? Thanks Jim In a message dated 97-12-03 00:34:15 EST, ghughes@sarnoff.com writes: << Dear Roy, =20 Drinking from a fire hose is expensive. =20 We have built 7 HFR cameras for White Sands Missile Range with the following characteristics: =20 * Thinned, back illuminated 1024 x 1024 pixel 32 port Split-FT CCD with = on chip CDS * 100% optical fill factor * Blooming control * Low transfer smear * 150 fps full resolution, 300 fps with 2:1 vertical binning * Variable frame rate from 30 to 300 fps * 32 (12 bit) ADCs * 24 fiber-optic cables deliver 12 bit digital video to a proprietary vi= deo processor * 1.9 Gb/sec sustained video data rate, 3.8 Gb/sec capability * Video also re-formatted for RS-170 display at 512 x 480 pixels for all frame rates =20 For details see "1024 x 1024 pixel high frame rate digital CCD camera", G.W. Hughes et. al, Proceedings of SPIE, Vol. 2869, 1997, 22nd Intl. Congress on High Speed Photography and Photonics, 27 Oct - 1 Nov. 1996. =20 At 03:27 PM 12/2/97 -0500, you wrote: >Mail*Link=AE SMTP high-speed cameras > >Posted to CCD-world: >-+-+-+- >Dear charge-transfer enthusiasts, > Here at NSO's GONG project we are upgrading the camera and video d= ata >acquisition systems for the network from a 256x256 resolution system to= a >1024 squared array sensor (Thomson THX7887). Output is four channels of= 12 >bit data, 60 frames per second, 20 MHz pixel clock. If you use two byte= s to >store 12 bits, it works out to 120 Mbytes/sec that have to be moved aro= und. >Not only that, but our data acquisition involves co-adding images into >three integration buffers (the camera operation is coordinated with a >rotating polarizer such that three frame times corresponds to one rotat= ion >of the polarizer) so that in a one minute integration time we produce >resulting images with 23 bit pixels (aw, gee, go ahead and call it thre= e >bytes per pixel). We're still trying to decide "Build or Buy, Build or >Buy?". Our inquiries have been directed to the usual suspects in the im= age >processing hardware field and also to folks offering VME compatible DSP >boards (we'd like to stick with VME architecture). The responses we've >gotten back have generally been budget-busters. We may be compelled to >home-brew a solution. If anyone has faced a similar problem of drinking >from a fire hose, I'd appreciate receiving some pearls of wisdom based = upon >your experiences. > Thanks a lot for any input. > - Roy Tucker > >-+-+-+- >For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. > >------------------ RFC822 Header Follows ------------------ >Received: by maca.sarnoff.com with ADMIN;2 Dec 1997 15:27:35 -0500 >Received: from niu.cfht.hawaii.edu (niu.cfht.hawaii.edu [128.171.80.58]= ) by nova.sarnoff.com (8.6.12/8.6.12) with ESMTP id PAA18654 for ; Tue, 2 Dec 1997 15:26:08 -0500 >Received: from uwila.cfht.hawaii.edu ([128.171.80.50]) > by niu.cfht.hawaii.edu (Post.Office MTA v3.1.2 > release (PO203-101c) ID# 0-43928U200L100S0) with SMTP id AAA2= 2499 > for ; > Tue, 2 Dec 1997 10:15:48 -1000 >Received: from noao.edu by uwila.cfht.hawaii.edu with SMTP id AA24557 > (5.65c/IDA-1.4.4 for ); Tue, 2 Dec 1997 10:16:04 -1000 >Received: from orion.tuc.noao.edu (orion.tuc.noao.edu [140.252.1.22]) > by noao.edu (8.8.7/8.8.5/SAG-14May97) with ESMTP id NAA28441 > for ; Tue, 2 Dec 1997 13:15:58 -0700 (MST) >Received: from selket.tuc.noao.edu (selket.tuc.noao.edu [140.252.8.19]) > by orion.tuc.noao.edu (8.8.6/8.8.6/SAG-11Jul96) with SMTP id NAA20931 > for ; Tue, 2 Dec 1997 13:15:57 -0700 (MST) >Message-Id: <3.0.5.32.19971202131537.007b4470@orion> >Date: Tue, 02 Dec 1997 13:15:37 -0700 >To: CCD-world@cfht.hawaii.edu >From: Roy Tucker >Subject: high-speed cameras >Mime-Version: 1.0 >Content-Type: text/plain; charset=3D"us-ascii" >Reply-To: CCD-world@cfht.hawaii.edu > > > > =20 Regards, Gary Hughes Sarnoff Corporation 609/734-3056 609/734-2565 (fax) =20 -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From MYPIXEL at aol.com Wed Dec 3 11:30:34 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:23 2004 Subject: LOCKUP Message-ID: <971203103033_1644519035@mrin44.mail.aol.com> Posted to CCD-world: -+-+-+- Not sure if this is appropriate for CCD world but . .. Problems with general GATES-95 application lock-up. . . . try this .. . worked wonders for us and new 233 MHz computers. Jim Go to Start on desk top Hit run Type SYSEDIT (Enter that . . . and you'll see a bunch of windows) Choose the C:\windows\system.int window Then look for [DISPLAY] about 3/4 of the way down list Under [DISPLAY] add three lines (on my machine there was nothing under display) devbmp = 0 stretchengine = 0 stretchblt = 0 Then close window by hitting X at upper right hand corner. It will ask you if you want to save .. . hit yes. The problem might be fixed after rebooting. Jim -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From MYPIXEL at aol.com Wed Dec 3 11:25:07 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:23 2004 Subject: high-speed cameras Message-ID: <971203102507_1373746955@mrin47> Posted to CCD-world: -+-+-+- In a message dated 97-12-02 15:50:13 EST, tucker@noao.edu writes: << From: tucker@noao.edu (Roy Tucker) Reply-to: CCD-world@cfht.hawaii.edu To: CCD-world@cfht.hawaii.edu Posted to CCD-world: -+-+-+- Dear charge-transfer enthusiasts, Here at NSO's GONG project we are upgrading the camera and video data acquisition systems for the network from a 256x256 resolution system to a 1024 squared array sensor (Thomson THX7887). Output is four channels of 12 bit data, 60 frames per second, 20 MHz pixel clock. If you use two bytes to store 12 bits, it works out to 120 Mbytes/sec that have to be moved around. >> Roy .. . that has got Pluto beat. . . amazing. We are strapped a bit because of the thinned Pluto. . it doesn't like to run fast (old dog). JJ -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From MYPIXEL at aol.com Wed Dec 3 11:15:37 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:23 2004 Subject: PLUTO HSS CCD Message-ID: <971203101537_380973304@mrin83.mail.aol.com> Posted to CCD-world: -+-+-+- In a message dated 97-12-02 15:37:51 EST, HOFFBEMG@sterlingdi.com writes: Mike, Please contact George Williams (GeorgeW@pvinc.com) about Pluto HSS camera system. There are two Pixel Visions . .. . .. we are working the Sandbox CCDs (Pixel Vision South - Surf City - Huntington Beach, Ca.) and George heads up cameras (Pixel Vision North - Green City - Beaverton, Or.). Yes, each channel is moving at 10 Mpixels/sec (I believe at 12 bits). The computer interface is pretty special to take data in at that rate (PCI , Fire cable, things I don't understand). They have a Pluto up there now working at that rate. Our main activity here (PVS) is to get the verticals moving at 1 micro-sec per line for a thinned CCD (required for split-frame transfer). The CCD physics is most interesting. I hope to share some of that info to CCD World (amazing stuff). I think one of these days astronomers will want faster CCDs - e.g., ADAPTIVE OPTICS seems to be pushing vertical speed. Anyway, thanks for your interest in Pluto. Jim << Posted to CCD-world: -+-+-+- What sort of data acquisition system has been designed to capture the data from this CCD? At 100 ns / pixel with 4 outputs, you are generating pixels at a rate of about 40 Mpixels/second. I assume that the data is digitized from 12 to 16 bits, which means that the data rate is 80 Mbytes/second. MIKE >> -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From ghughes at sarnoff.com Tue Dec 2 16:55:48 1997 From: ghughes at sarnoff.com (GARY HUGHES) Date: Thu Jul 29 11:54:23 2004 Subject: high-speed cameras In-Reply-To: Message-ID: <3.0.3.32.19971202155548.0070409c@postoffice.sarnoff.com> Posted to CCD-world: -+-+-+- Dear Roy, Drinking from a fire hose is expensive. We have built 7 HFR cameras for White Sands Missile Range with the following characteristics: * Thinned, back illuminated 1024 x 1024 pixel 32 port Split-FT CCD with on chip CDS * 100% optical fill factor * Blooming control * Low transfer smear * 150 fps full resolution, 300 fps with 2:1 vertical binning * Variable frame rate from 30 to 300 fps * 32 (12 bit) ADCs * 24 fiber-optic cables deliver 12 bit digital video to a proprietary video processor * 1.9 Gb/sec sustained video data rate, 3.8 Gb/sec capability * Video also re-formatted for RS-170 display at 512 x 480 pixels for all frame rates For details see "1024 x 1024 pixel high frame rate digital CCD camera", G.W. Hughes et. al, Proceedings of SPIE, Vol. 2869, 1997, 22nd Intl. Congress on High Speed Photography and Photonics, 27 Oct - 1 Nov. 1996. At 03:27 PM 12/2/97 -0500, you wrote: >Mail*Link? SMTP high-speed cameras > >Posted to CCD-world: >-+-+-+- >Dear charge-transfer enthusiasts, > Here at NSO's GONG project we are upgrading the camera and video data >acquisition systems for the network from a 256x256 resolution system to a >1024 squared array sensor (Thomson THX7887). Output is four channels of 12 >bit data, 60 frames per second, 20 MHz pixel clock. If you use two bytes to >store 12 bits, it works out to 120 Mbytes/sec that have to be moved around. >Not only that, but our data acquisition involves co-adding images into >three integration buffers (the camera operation is coordinated with a >rotating polarizer such that three frame times corresponds to one rotation >of the polarizer) so that in a one minute integration time we produce >resulting images with 23 bit pixels (aw, gee, go ahead and call it three >bytes per pixel). We're still trying to decide "Build or Buy, Build or >Buy?". Our inquiries have been directed to the usual suspects in the image >processing hardware field and also to folks offering VME compatible DSP >boards (we'd like to stick with VME architecture). The responses we've >gotten back have generally been budget-busters. We may be compelled to >home-brew a solution. If anyone has faced a similar problem of drinking >from a fire hose, I'd appreciate receiving some pearls of wisdom based upon >your experiences. > Thanks a lot for any input. > - Roy Tucker > >-+-+-+- >For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. > >------------------ RFC822 Header Follows ------------------ >Received: by maca.sarnoff.com with ADMIN;2 Dec 1997 15:27:35 -0500 >Received: from niu.cfht.hawaii.edu (niu.cfht.hawaii.edu [128.171.80.58]) by nova.sarnoff.com (8.6.12/8.6.12) with ESMTP id PAA18654 for ; Tue, 2 Dec 1997 15:26:08 -0500 >Received: from uwila.cfht.hawaii.edu ([128.171.80.50]) > by niu.cfht.hawaii.edu (Post.Office MTA v3.1.2 > release (PO203-101c) ID# 0-43928U200L100S0) with SMTP id AAA22499 > for ; > Tue, 2 Dec 1997 10:15:48 -1000 >Received: from noao.edu by uwila.cfht.hawaii.edu with SMTP id AA24557 > (5.65c/IDA-1.4.4 for ); Tue, 2 Dec 1997 10:16:04 -1000 >Received: from orion.tuc.noao.edu (orion.tuc.noao.edu [140.252.1.22]) > by noao.edu (8.8.7/8.8.5/SAG-14May97) with ESMTP id NAA28441 > for ; Tue, 2 Dec 1997 13:15:58 -0700 (MST) >Received: from selket.tuc.noao.edu (selket.tuc.noao.edu [140.252.8.19]) > by orion.tuc.noao.edu (8.8.6/8.8.6/SAG-11Jul96) with SMTP id NAA20931 > for ; Tue, 2 Dec 1997 13:15:57 -0700 (MST) >Message-Id: <3.0.5.32.19971202131537.007b4470@orion> >Date: Tue, 02 Dec 1997 13:15:37 -0700 >To: CCD-world@cfht.hawaii.edu >From: Roy Tucker >Subject: high-speed cameras >Mime-Version: 1.0 >Content-Type: text/plain; charset="us-ascii" >Reply-To: CCD-world@cfht.hawaii.edu > > > > Regards, Gary Hughes Sarnoff Corporation 609/734-3056 609/734-2565 (fax) -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From tucker at noao.edu Tue Dec 2 14:15:37 1997 From: tucker at noao.edu (Roy Tucker) Date: Thu Jul 29 11:54:23 2004 Subject: high-speed cameras Message-ID: <3.0.5.32.19971202131537.007b4470@orion> Posted to CCD-world: -+-+-+- Dear charge-transfer enthusiasts, Here at NSO's GONG project we are upgrading the camera and video data acquisition systems for the network from a 256x256 resolution system to a 1024 squared array sensor (Thomson THX7887). Output is four channels of 12 bit data, 60 frames per second, 20 MHz pixel clock. If you use two bytes to store 12 bits, it works out to 120 Mbytes/sec that have to be moved around. Not only that, but our data acquisition involves co-adding images into three integration buffers (the camera operation is coordinated with a rotating polarizer such that three frame times corresponds to one rotation of the polarizer) so that in a one minute integration time we produce resulting images with 23 bit pixels (aw, gee, go ahead and call it three bytes per pixel). We're still trying to decide "Build or Buy, Build or Buy?". Our inquiries have been directed to the usual suspects in the image processing hardware field and also to folks offering VME compatible DSP boards (we'd like to stick with VME architecture). The responses we've gotten back have generally been budget-busters. We may be compelled to home-brew a solution. If anyone has faced a similar problem of drinking from a fire hose, I'd appreciate receiving some pearls of wisdom based upon your experiences. Thanks a lot for any input. - Roy Tucker -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From tmca Tue Dec 2 10:29:48 1997 From: tmca (Tim Abbott) Date: Thu Jul 29 11:54:23 2004 Subject: PLUTO HSS CCD In-Reply-To: from "Michael Hoffberg" at Dec 2, 97 08:45:21 am Message-ID: <199712021929.JAA22297@kuanalu.cfht.hawaii.edu> Posted to CCD-world: -+-+-+- Hi Michael, With the new CCD-world system, if you do not send your contribution from your registered email address (hoffberg@aps.anl.gov), then it does not get forwarded until it gets the OK from me. (This is to filter out the junk email we all loathe.) This is no problem at this end, but it does mean there will be a delay. Cheers, Tim Abbott Moderator, CCD-world. Michael Hoffberg writes: > > Posted to CCD-world: > -+-+-+- > What sort of data acquisition system has been designed to capture the data from > this CCD? > > At 100 ns / pixel with 4 outputs, you are generating pixels at a rate of about > 40 Mpixels/second. I assume that the data is digitized from 12 to 16 bits, > which means that the data rate is 80 Mbytes/second. > > MIKE > > ------------------------------------------------------------------ > Posted to CCD-world: > -+-+-+- > Four your information . . . > > Find below specfications for a new High Speed Scientific 1024(H) x 2048 (V) > CCD that Pixel Vision and SITe has recently developed on Sandbox (current > performance given). The primary focus has been to achieve 30 frames/sec split > frame transfer operation in conjunction with backside illumination (1 > micro-sec line transfer time is the goal). This work will be discussed in an > upcoming San Jose SPIE paper. Improvements on performance parameters will > come from future Sandbox runs (e.g., anti-blooming, reducing clock levels, > MPP, improved MTF and noise). The Pluto CCD has been recently coated by Mike > Lessor for QE improvement. > > I'm curious. . . are astronomers yet observing vertical speed problems (ie. > full well reduction) for backside devices? This is a new area of development > as thinned devices are clocked at faster rates. > > Jim Janesick > > > PLUTO - 12 HSS CCD SPECIFICATIONS (NOV 1997) > [etc...] > > > > > > > > > > > > > > > > > > > > > -+-+-+- > For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. > -- Timothy M. C. Abbott, Ph.D. http://www.cfht.hawaii.edu/~tmca/ Resident Astronomer tmca@cfht.hawaii.edu Canada-France-Hawaii Telescope Tel: +1 808 885 7944 Box 1597, Kamuela, HI 96743 Fax: +1 808 885 7288 -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From HOFFBEMG at sterlingdi.com Tue Dec 2 09:45:21 1997 From: HOFFBEMG at sterlingdi.com (Michael Hoffberg) Date: Thu Jul 29 11:54:23 2004 Subject: PLUTO HSS CCD Message-ID: Posted to CCD-world: -+-+-+- What sort of data acquisition system has been designed to capture the data from this CCD? At 100 ns / pixel with 4 outputs, you are generating pixels at a rate of about 40 Mpixels/second. I assume that the data is digitized from 12 to 16 bits, which means that the data rate is 80 Mbytes/second. MIKE ------------------------------------------------------------------ Posted to CCD-world: -+-+-+- Four your information . . . Find below specfications for a new High Speed Scientific 1024(H) x 2048 (V) CCD that Pixel Vision and SITe has recently developed on Sandbox (current performance given). The primary focus has been to achieve 30 frames/sec split frame transfer operation in conjunction with backside illumination (1 micro-sec line transfer time is the goal). This work will be discussed in an upcoming San Jose SPIE paper. Improvements on performance parameters will come from future Sandbox runs (e.g., anti-blooming, reducing clock levels, MPP, improved MTF and noise). The Pluto CCD has been recently coated by Mike Lessor for QE improvement. I'm curious. . . are astronomers yet observing vertical speed problems (ie. full well reduction) for backside devices? This is a new area of development as thinned devices are clocked at faster rates. Jim Janesick PLUTO - 12 HSS CCD SPECIFICATIONS (NOV 1997) [etc...] -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From MYPIXEL at aol.com Tue Dec 2 03:39:30 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:23 2004 Subject: PLUTO HSS CCD Message-ID: <971202023930_-1774796293@mrin44.mail.aol.com> Posted to CCD-world: -+-+-+- Four your information . . . Find below specfications for a new High Speed Scientific 1024(H) x 2048 (V) CCD that Pixel Vision and SITe has recently developed on Sandbox (current performance given). The primary focus has been to achieve 30 frames/sec split frame transfer operation in conjunction with backside illumination (1 micro-sec line transfer time is the goal). This work will be discussed in an upcoming San Jose SPIE paper. Improvements on performance parameters will come from future Sandbox runs (e.g., anti-blooming, reducing clock levels, MPP, improved MTF and noise). The Pluto CCD has been recently coated by Mike Lessor for QE improvement. I'm curious. . . are astronomers yet observing vertical speed problems (ie. full well reduction) for backside devices? This is a new area of development as thinned devices are clocked at faster rates. Jim Janesick PLUTO - 12 HSS CCD SPECIFICATIONS (NOV 1997) FABRICATION PROCESS 1). Silicon wafers: 20-micron, 30-40 ohm-cm, four-inch epitaxial silicon. 2). LOCOS, 3-phase, buried channel, LDD, backside- illumination. 3). Gate insulator: oxide (500 A) / nitride (500 A). 4). Poly gate thickness < 4000 A. 5). Poly gate overlaps > 1-micron. ARCHITECTURE 1). Format 2048(V) x 1024(H). 2). Split frame transfer. 3). Pixel shape: square. 4). Pixel spacing: 12-microns. 5). Channel-stop width: 2.5-microns. 6). Quad vertical sections clocked from both sides of the array. 7). Two split horizontal registers. 8). Four extended pixels per horizontal register. 9). Four output summing gates. 10). Four last gates. 11). Four high-speed, floating diffusion, LDD, buried-channel, two- stage, MOSFET amplifiers. VERTICAL REGISTER PERFORMANCE 1). Sensitivity (sensed electrons per incident photon): 4000 A > 0.65 6000 A > 0.85 8000 A > 0.50 2). CTE > 0.99995 (1620 e- point source). 3). Dark current generation (at 300 K): < 1 nA/cm2 (partially-inverted). 4). Vertical full well capacity > 200,000 e- ( >12 micro-sec line time). 5). Vertical MTF (Nyquist / 4000 A) : > 0.35 6). Pixel nonuniformity: < 2%. 7). Line transfer time (full well): < 12 micro-sec. 8). Array flatness < 20-microns. HORIZONTAL REGISTER PERFORMANCE 1). CTE > 0.99995 (1620 e- point source). 2). Horizontal full well capacity > 300,000 e- (100 ns pixel rate). 3). Horizontal pixel transfer time < 100 ns. ON-CHIP AMPLIFIER PERFORMANCE 1). Readout noise (> 200 kpixels sec): < 0.008 (pixel rate)^1/2 2). On-chip amplifier gain > 0.8 V/V. 3). Sensitivity: > 3.0 micro-volts/e-. 4). Video dump time constant (Cl = 5 pf): < 25 ns, 5). Nonlinearity: < 1% over dynamic range. TYPICAL OPERATING CLOCK AND DC BIAS VOLTAGES 1). Output Drain = 22 V 2). Reference = 16.5 V 3). Last Gate = - 2.5 V 4). Reset Gate = -1 V to 15 V 5). Horizontal Clocks (non-inverted) = - 5 V to + 5 V 6). Vertical Clocks (partial inversion) = -10 V to + 5 TEST CONDITIONS Unless otherwise noted all specifications are at 300 K. <><><><><><><><><><><><><><><><><><><><><><><><><> -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From MYPIXEL at aol.com Mon Dec 1 11:28:09 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:23 2004 Subject: CCD-world: Re: Optimum CCD Set-up, from Mingzhi Wei Message-ID: <971201102809_-1666351768@mrin83.mail.aol.com> Posted to CCD-world: -+-+-+- In a message dated 97-11-25 23:43:35 EST, tmca@cfht.hawaii.edu writes: < Hi Jim, Thank you very much for your comments. They are very helpful. Followings are my more comments. Mingzhi *******jj Here are some comments back . . . Jim Janesick *******jj ----- These measurements are done with very wide(300us) and long rising time(100us) vertical clocks Mingzhi ----- ******jj I gather the long widths are exclusively for spurious charge. That should be sufficient based on my experience. However, I'm assuming non RC waveshaping. Remember you want the clock to take off slowly at first and then speed up towards the end of the rising edge (RC does the opposite). By the way, one should see more spurious on the edges of the CCD than its middle (due to poly resistance and waveshaping in the middle of the CCD). ******jj ----- The on-chip amplifiers of LL CCID20 CCDs got non-linear and saturation before pixels reaching their full well. We got linear range of amplifier only up to 115 ke- (sorry, I should not use "full well" for this) Mingzhi ----- *****jj Might want to look into that nonlinearity problem. I wonder. . does it have to do with Lincoln's high sensitivity (ie., 20 uV/e-)? That is, a 2.3 V change on the gate for 115 k e-. That swing might cause the linearity. *****jj ------- What you mean that "residual image effects in the image you are reading (i.e., tails)." Mingzhi -------- ******jj Recall you can reach SFW in the image you are reading out (i.e., charge interacts with surface states). . . The only way to eliminate that is by inverting. *****jj --------- (1) Is it "high level vertical CTE"? Mingzhi ------- ******jj Yes, it is called Surface Full Well (SFW). Results in deferred charge. ******jj -------- (2) If you mean that it happens because of the special erase clocks. why? We setup the special erase clocks 0v to -12v and all inverted. Mingzhi -------- *****jj No *****jj ------- (3) If you mean that it happens because we do not inverted clocks during read out time. We have no choice because LL CCDs are not MPP devices and this is why we need special inverted erase clocks to remove the residual images. Mingzhi -------- ******jj No, partial inversion (two phases low - one phase high) will eliminate surface residual image (no need for MPP either). Just make sure the barriers go into inversion. No special clocks are required. *******jj --------- Actually we did not see any vertical tail in the images which lower than 163 ke- and we saw very sharp residual image pattern even we used regular noninverted erase clocks. Mingzhi ---------- *******jj Taking barriers out of inversion will drastically reduce full well .. . again partially inverted (say -8 to +5) will achieve highest full well possible and eliminate residual image. The only thing to worry about is spurious (use proper waveshaping here). ********jj ------ We are still do optimization of the special erase clocks, such as voltages, shape, min. requirest erase time and erase procedure. But now we don't worry causing spurious charge and other problem, because this optimization is independent. MIngzhi ------ ******jj ? Keep it simple ******jj ----- According to our experiment results: (our vertical clocks already very wide and slow rising edge) (1) if we use Vv=2v,-6v for vertical clocks we got spurious charge: 0.42e- and residual image: 9.16e- (100sec integration time) (2) if we use vv=2v,-8v we got spurious charge: 6.16e- and residual image: 3.5e- (100sec) if we use special erase clocks: we got spurious charge 0.42e- and residual image: 1.1e- (100sec) Which do you prefer? *******jj Always . . . partial inversion to keep things simple and optimum. Take spurious charge off to the side and work on it. Don't give up .. you are down to 6 e-.. a little more waveshaping should do it. ******jj -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From tmca Wed Nov 26 15:28:37 1997 From: tmca (Tim Abbott) Date: Thu Jul 29 11:54:23 2004 Subject: CCD-world upgrade Message-ID: <19971127002838.AAA28711@niu.cfht.hawaii.edu> Posted to CCD-world: -+-+-+- Dear CCD-world, The CCD-world emailing list is now running through the mailing-list manager software "Post.Office" from Software.Com [tm]. This is a new software package at CFHT and so there may be some problems, although we have tested the system as thoroughly as we can. If there are problems, Post.Office will be turned off immediately and we shall return to the manual methods until the problems are fixed. There is a web interface through which you can manage your own subscription. This is not yet available at CFHT, but I shall add it to the CCD-world web pages as soon as I can. In the meantime, you can now treat CCD-world as if it were a major-domo style mailing list via the address ccd-world-request@cfht.hawaii.edu. Send the one-line message "help" to this address for information. The mailing list is currently configured as follows: * Posting by subscribers is unmoderated and immediate * Posting by non-subscribers is moderated (this means I get *all* the junk mail and you get none...) * the following header line is added to CCD-world mailings: Reply-To: CCD-world@cfht.hawaii.edu Hopefully this will eliminate the bounced messages contributors have been receiving from some machines. * CCD-world subscriber emails are not expanded in sent mail. * Maximum message size: 500K * Subscription requests are verified and moderated. * Unsubscribing is verified and moderated (so no-one can unsubscribe you except yourself). * Subscribers can obtain a full list of CCD-world subscribers. (Be good!) * You can select digest delivery if you like. Kudos to Bob Link at CFHT for getting this up and running so quickly. Enjoy, Tim Abbott Moderator, CCD-world. -- Timothy M. C. Abbott, Ph.D. http://www.cfht.hawaii.edu/~tmca/ Resident Astronomer tmca@cfht.hawaii.edu Canada-France-Hawaii Telescope Tel: +1 808 885 7944 Box 1597, Kamuela, HI 96743 Fax: +1 808 885 7288 -+-+-+- For information about CCD-world, send email to owner-CCD-world@cfht.hawaii.edu. From wmz at ucolick.org Tue Nov 25 17:21:24 1997 From: wmz at ucolick.org (Mingzhi Wei) Date: Thu Jul 29 11:54:23 2004 Subject: Optimum CCD Set-up Message-ID: Hi Jim, Thank you very much for your comments. They are very helpful. Followings are my more comments. Mingzhi >>******** >>Mingzhi .. . . some comments below. . . Lincoln is looking good for you >>guys .. . Jim Janesick >> >>****** >> >>In a message dated 97-11-12 18:26:27 EST, wmz@ucolick.org writes: >> >> >> Hi all, >> We've experimented Lincoln CCID20 2kx4k thin CCDs for optimization >> of high full well, low spurious charge, low residual image and low dark >>current >> at Lick Observatory CCD lab. >> Here I like to present some results: >> >> (1) spurious charge: >> These measurements are taken after whole night continuous reading out >> at very low temperature(-140c) to eliminate dark current and residual >>images. >> We took 1 second dark and measured the averages of top, middle and bottom >>areas >> of the CCD. >> >>********* >> >>Theoretically dark current at -140 C translates to less than 0.0004 >>e/sec/pixel for a 10,000 nA/cm^2 (300K) CCD. Lincoln I'm sure must have a >>figure of merit of less that 1 nA/cm^2 indicating that the dark level would >>be < 0.00000004 e-/sec ... . isn't -140 C over kill? Cooling this low may >>cause problems for CTE, QE and spurious charge. - 100 C operation should be >>sufficient. >> >>******** ----- -140 C was not our operation temperature. It was one of our test temperature. We tested the LL CCDs at -90c,-100c,-110c and -140c. We needed the worst condition of residual image and spurious charges and saw if our special erase clocks could improve something. Mingzhi ----- >> Vertical voltages top middle bottom >> 4v,-4v 0.32e 0.49e 0.42e >> 2v,-6v 0.41e 0.56e 0.41e >> 2v,-8v 3.38e 5.37e 6.16e >> 4v,-6v 4.49e 6.87e 8.91e >> 2v,-10v 6.18e 17.9e 29.5e >> 4v,-8v 57.1e 88.8e 119.9e >> >>****** >>Appears to be spurious .. . are you fully waveshaped? >>****** ----- These measurements are done with very wide(300us) and long rising time(100us) vertical clocks Mingzhi ----- >> (2) Full well >> >> Full wells of these CCD are eliminated by high gain on-chip amplifier, >> it was about 115ke-. >> >>***** >>Not sure what you mean that full well can be eliminated by amplifier . .. ? >>******* ----- The on-chip amplifiers of LL CCID20 CCDs got non-linear and saturation before pixels reaching their full well. We got linear range of amplifier only up to 115 ke- (sorry, I should not use "full well" for this) Mingzhi ----- >> However Lincoln CCDs are not MPP devices, if we set Vv=2v,-6v and use >>regular >> nonmpp erasing clocks, we got high residual image after a very bright >> exposure. and the residual image lived for very long time(a few hours). >> More negative lower rails of vertical clocks will improve it, >> but still not good enough and will get high spurious charge too. >> >>***** >>Increase clock widths for more waveshaping >>**** >> >> Our Solution is: >> If CCD exposures to very bright light, >> Run a special erasing clocks before we start regular >> nonmpp erasing, exposuring and reading out. >> >>******* >>You will get residual image effects in the image you are reading (i.e., >>tails). Try to keep the CCD inverted at all times. Keep it simple. >> >>If you ever get into clocked anti-blooming (CAB) you'll need to invert too. >> >>***** ------- What you mean that "residual image effects in the image you are reading (i.e., tails)." (1) Is it "high level vertical CTE"? It causes the image we are reading with tails(like poor vertical CTE) or leave a residual image with tails? They smear to up and down two directions or just one direction(tails)? (2) If you mean that it happens because of the special erase clocks. why? We setup the special erase clocks 0v to -12v and all inverted. (3) If you mean that it happens because we do not inverted clocks during read out time. We have no choice because LL CCDs are not MPP devices and this is why we need special inverted erase clocks to remove the residual images. Actually we did not see any vertical tail in the images which lower than 163 ke- and we saw very sharp residual image pattern even we used regular noninverted erase clocks. Mingzhi ----- >> >> (1) set Vv=0,-12v run MPP erasing clocks to fill SI/SIO interface with >>holes. >> High amplitude of erasing clocks and that non MPP device works under >> inverted mode will cause extra charges and floating charges will go >> everywhere on the CCD. It doesn't meter because another regular erasing >> procedure will follow it before exposure. >> >>****** >>-12 V is too high . . . excess voltage goes across oxide and may damage CCD. >>****** ------ We are still do optimization of the special erase clocks, such as voltages, shape, min. requirest erase time and erase procedure. But now we don't worry causing spurious charge and other problem, because this optimization is independent. MIngzhi ------ >> >> (2) set up Vv to regular voltages (2v,-6v) and normal nonmpp timing, >> do another erasing to clean out dark current and extra charges >> which generated by the special erasing >> (3) normal exposure and read out. >> >> followings are our test results: >> >> (1) Vv=2,-6 and regular nonmpp erasing clocks >> after taking an about 460ke- exposure with a bright pattern >> first 100sec residual image: 9.16e- >> second 100sec residual image: 4.00e- >> (2) with new erasing procedure: >> after taking an about 460ke- exposure with a bright pattern >> first 100sec residual image: 1.1e- >> second 100sec residual image: 0.7e- >> >>****** >>Bottom line .. . invert barriers at all times for maximum full well, no >>residual image, optimum pixel nonuniformity, and simplicity. Deal with >>spurious with waveshaping (LC network for a slow change of rising edge >>initially). >> ----- According to our experiment results: (our vertical clocks already very wide and slow rising edge) (1) if we use Vv=2v,-6v for vertical clocks we got spurious charge: 0.42e- and residual image: 9.16e- (100sec integration time) (2) if we use vv=2v,-8v we got spurious charge: 6.16e- and residual image: 3.5e- (100sec) if we use special erase clocks: we got spurious charge 0.42e- and residual image: 1.1e- (100sec) Which do you prefer? Adding different vertical clocks to special erase is not difficult for system like Leach Controller. We also plan to put this procedure to idle time(the breaks between every two exposures). So we don't need extra time to do the special erase. Mingzhi ----- From MYPIXEL at aol.com Mon Nov 24 02:33:24 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: Optimum CCD Set-up Message-ID: <971124013323_1813527687@mrin45.mail.aol.com> ******** Mingzhi .. . . some comments below. . . Lincoln is looking good for you guys .. . Jim Janesick ****** In a message dated 97-11-12 18:26:27 EST, wmz@ucolick.org writes: Hi all, We've experimented Lincoln CCID20 2kx4k thin CCDs for optimization of high full well, low spurious charge, low residual image and low dark current at Lick Observatory CCD lab. Here I like to present some results: (1) spurious chage: These measurements are taken after whole night continuous reading out at very low temperature(-140c) to eliminate dark current and residual images. We took 1 second dark and measured the averages of top, middle and bottom areas of the CCD. ********* Theoretically dark current at -140 C translates to less than 0.0004 e/sec/pixel for a 10,000 nA/cm^2 (300K) CCD. Lincoln I'm sure must have a figure of merit of less that 1 nA/cm^2 indicating that the dark level would be < 0.00000004 e-/sec ... . isn't -140 C over kill? Cooling this low may cause problems for CTE, QE and sprurious charge. - 100 C operation should be sufficient. ******** Vertical voltages top middle bottom 4v,-4v 0.32e 0.49e 0.42e 2v,-6v 0.41e 0.56e 0.41e 2v,-8v 3.38e 5.37e 6.16e 4v,-6v 4.49e 6.87e 8.91e 2v,-10v 6.18e 17.9e 29.5e 4v,-8v 57.1e 88.8e 119.9e ****** Appears to be spurious .. . are you fully waveshaped? ****** (2) Full well Full wells of these CCD are eliminated by high gain on-chip amplifier, it was about 115ke-. ***** Not sure what you mean that full well can be eliminated by amplifier . .. ? ******* However we fond that the pixel full well was very high. The start-blooming level is about 460ke- if vertical votages(Vv) are set to 2v,-6v and about 640ke- if Vv are set to 4v,-6v. ******* Maximum full well will occur when barriers are inverted. Full Well Transfer will tell you where the optimum positive voltage should be set (typically a couple of volts). Also note that thinned CCDs run slow vertically (because of lack of substrate) which can degrade full well. There are some tricks to circuvent this problem if necessary. ******* >From above results we can see that high amplitude of vertical clocks will cause high spurious chages, and upper rails of the vertical clocks are more critical. Vv=2v,-6v is the best setup for high full well and low spurious charge for these CCDs. ******* It is important to make sure the device is inverted or residual image will appear even in the image you are reading. Might need to increase vertical clock widths to add more waveshaping to eliminate spurious charge. **** However Lincoln CCDs are not MPP devices, if we set Vv=2v,-6v and use regular nonmpp erasing clocks, we got high residual image after a very bright exposure. and the residual image lived for very long time(a fer hours). More negative lower rails of vertical clocks will improve it, but still not good enough and will get high spurious charge too. ***** Increase clock widths for more waveshaping **** Our Solution is: If CCD exposures to very bright light, Run a special erasing clocks before we start regular nonmpp erasing,exposuring and reading out. ******* You will get residual image effects in the image you are reading (i.e., tails). Try to keep the CCD inverted at all times. Keep it simple. If you ever get into clocked anti-blooming (CAB) you'll need to invert too. ***** (1) set Vv=0,-12v run MPP erasing clocks to fill SI/SIO interface with holes. High amplitude of erasing clocks and that non MPP device works under inverted mode will cause extra charges and floating chages will go everywhere on the CCD. It doesn't meter because another regular erasing procedure will follow it before exposure. ****** -12 V is too high . . . excess voltage goes across oxide and may damage CCD. ****** (2) set up Vv to regular voltages (2v,-6v) and normal nonmpp timing, do another erasing to clean out dark current and extra charges which generated by the special erasing (3) normal exposure and read out. followings are our test results: (1) Vv=2,-6 and regular nonmpp erasing clocks after taking an about 460ke- exposure with a bright pattern first 100sec residual image: 9.16e- second 100sec residual image: 4.00e- (2) with new erasing procedure: after taking an about 460ke- exposure with a bright pattern first 100sec residual image: 1.1e- second 100sec residual image: 0.7e- ****** Bottom line .. . invert barriers at all times for maximum full well, no residual image, optimum pixel nonuniformity, and simplicity. Deal with spurious with waveshaping (LC network for a slow change of rising edge initially). ****** **** By the way, spurious charge increases with decreasing temperature. . . another reason for not going to -140 C. This is because hole mobility which increases impact ionization. ****** Mingzhi Wei -- UCO/Lick Observatory University of California Santa Cruz, CA 95064 USA Voice: 408-459-4911 FAX: 408-426-3115 email: wmz@ucolick.org From dji at ast.cam.ac.uk Wed Nov 19 19:17:40 1997 From: dji at ast.cam.ac.uk (Derek Ives) Date: Thu Jul 29 11:54:24 2004 Subject: hermetic connectors Message-ID: Hi all, I was wondering if anyone in CCD WORLD can help. We require, on a short timescale, a 61 way, 4 hole square mounted, hermetic connector such as those supplied by Amphenol, specifically with part no. 62GB12H2461P3. We only need 2 off, but to purchase them in the U.K. would cost >1000 dollars ( minimum order quantity) and there is a 12 week delivery timescale. I am hoping that someone out there may have one or two sitting in a bottom drawer. We will, of course, pay for them. I must confess that this is for an IR camera. Regards, Derek Ives **************************************************************** E-mail: dji@ast.cam.ac.uk Machine: Kria.ast.cam.ac.uk Royal Greenwich Observatory, Madingley Road, Cambridge, CB3 0EZ, UK. Phone: +44 (0) 1223- 374000 \direct phone- 374824 \RGO Fax- 374700 **************************************************************** From wmz at ucolick.org Wed Nov 12 10:43:40 1997 From: wmz at ucolick.org (Wei Ming Zhi) Date: Thu Jul 29 11:54:24 2004 Subject: spurious charge and residual image Message-ID: Hi all, We've experimented Lincoln CCID20 2kx4k thin CCDs for optimization of high full well, low spurious charge, low residual image and low dark current at Lick Observatory CCD lab. Here I like to present some results: (1) spurious chage: These measurements are taken after whole night continuous reading out at very low temperature(-140c) to eliminate dark current and residual images. We took 1 second dark and measured the averages of top, middle and bottom areas of the CCD. Vertical voltages top middle bottom 4v,-4v 0.32e 0.49e 0.42e 2v,-6v 0.41e 0.56e 0.41e 2v,-8v 3.38e 5.37e 6.16e 4v,-6v 4.49e 6.87e 8.91e 2v,-10v 6.18e 17.9e 29.5e 4v,-8v 57.1e 88.8e 119.9e (2) Full well Full wells of these CCD are eliminated by high gain on-chip amplifier, it was about 115ke-. However we fond that the pixel full well was very high. The start-blooming level is about 460ke- if vertical votages(Vv) are set to 2v,-6v and about 640ke- if Vv are set to 4v,-6v. >From above results we can see that high amplitude of vertical clocks will cause high spurious chages, and upper rails of the vertical clocks are more critical. Vv=2v,-6v is the best setup for high full well and low spurious charge for these CCDs. However Lincoln CCDs are not MPP devices, if we set Vv=2v,-6v and use regular nonmpp erasing clocks, we got high residual image after a very bright exposure. and the residual image lived for very long time(a fer hours). More negative lower rails of vertical clocks will improve it, but still not good enough and will get high spurious charge too. Our Solution is: If CCD exposures to very bright light, Run a special erasing clocks before we start regular nonmpp erasing,exposuring and reading out. (1) set Vv=0,-12v run MPP erasing clocks to fill SI/SIO interface with holes. High amplitude of erasing clocks and that non MPP device works under inverted mode will cause extra charges and floating chages will go everywhere on the CCD. It doesn't meter because another regular erasing procedure will follow it before exposure. (2) set up Vv to regular voltages (2v,-6v) and normal nonmpp timing, do another erasing to clean out dark current and extra charges which generated by the special erasing (3) normal exposure and read out. followings are our test results: (1) Vv=2,-6 and regular nonmpp erasing clocks after taking an about 460ke- exposure with a bright pattern first 100sec residual image: 9.16e- second 100sec residual image: 4.00e- (2) with new erasing procedure: after taking an about 460ke- exposure with a bright pattern first 100sec residual image: 1.1e- second 100sec residual image: 0.7e- Mingzhi Wei -- UCO/Lick Observatory University of California Santa Cruz, CA 95064 USA Voice: 408-459-4911 FAX: 408-426-3115 email: wmz@ucolick.org From MYPIXEL at aol.com Tue Nov 11 11:44:06 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: Parallel clocking issues Message-ID: <971111104402_1592646827@mrin47> ****** JJ here .. . Ralf. . . right on the money with how full well works . . the best write up I've seen. . . we typically sum things up by generating a Full Well Transfer curve. A plot of full well versus positive clock swing is the main plot. A family of curves can also be generated for negative clock swing, MPP clock swing, and line transfer time for high speed applications. The curve can be generated in a few minutes depending on set up. The MPP phase could also be driven to -8 V as other clocks. . . there is no difference in full well. I guess there is still some argument on the positive level. The MPP implant can come in three flavors: less than optimum, optimum and over optimum for the implant itself. Question .. . for your full well transfer do you see a flat topped response ? That is, there is no change in full well with positive swing over a large voltage range (this region is limited by how much charge can be stored in phases 1 and 2 with all phases inverted). This would indicate that there was not enough MPP implant for optimum full well. I believe Loral was fabricating 2k x 2k CCDs at that time that way. The positive level doesn't make a big difference in this case. For the other cases it does. Watch out for CCDs that have a negative optimum full well point. . . you almost have one here (some CCD drivers have difficulties under this condition). CCD manufacturers are now starting to increase array doping. This will push the optimum full well point out to a higher positive clock swing. But the change is worth it. For example our Pluto CCD is coming in a 300,000 e- for a 12 micron pixel. Also, manufacturers are reducing high temp process steps . . . this will make a shallower channel and push the optimum point the other way. Your CCD for example appears to have built with a low temp process (my guess 1050 for one hour or less - in fact I recall this to be the case) Again great job! Jim ******* In a message dated 97-11-10 14:56:11 EST, rkohley@astro.uni-bonn.de writes: << Subj: Parallel clocking issues Date: 97-11-10 14:56:11 EST From: rkohley@astro.uni-bonn.de (Ralf Kohley) To: ccd-world@cfht.hawaii.edu Hi Roger and all, we've experimented with finding an optimum setup for the parallel clocks, which is not that trivial and even slightly different from device to device of the same kind of CCD. I tried to summerize some effects in my SPIE 95 article (Vol. 2415). There are different kinds of full well limitation to be considered: example: thick Loral 2k x 2k, 15 um 1. Integration full well Do you operate in the bloomed or surface full well regime? a) Bloomed full well (less positive voltages in upper rail, say between 0 and 1.4 V): Blooming occurs before electrons reach the surface (Si-Si02 interface) ( < 200000 e- ) b) Surface full well (more positive voltages in upper rail, say between 1.4 and 6 V): Blooming occurs at very high values ( >>200000 e-), but electrons reach the surface much before. => residual images c) Optimum full well "intersection of surface and bloomed full well" Blooming occurs just at the moment when electrons reach the surface, noramlly the best ( 1.4 V leading to 200000 e- capacity ) 2. Transport full well (parallel clocks) Again, do you operate in the bloomed or surface full well regime? Normally during integration on a MPP-CCD, the additionally doped phase plays the role as the barrier (-8 V or whatever). During transport it also becomes a collecting potential, but the well is not as deep as for the other two phases. We found a difference of +2.5 V, which we use as an offset for this particular phase. I believe, that most full well limitation arise from transport rather then from integration. a) Bloomed full well Blooming occurs, but no smearing b) Surface full well No blooming, but smearing of a part of the charge due to bad CTE of charge transported along the surface. c) Optimum full well We reach optimum full well with P1: -8 V to +1.4 V P2: -8 V to +1.4 V P3: -5.5 V to +3.9 V 3. Transport full well (parallel transfer gate) Are the transfer gates in both directions equally doped? If not and you use a fixed voltage for the transfer gates, you can get different full wells in both directions. On inversion: I did a test with switching voltages between integration and read-out. Take a look at http://www.astro.uni-bonn.de/~rkohley/paper/eso96.html More on spurious charge: We don't use tri-level clocking during read-out, since the the production of spurious charge scales with clocking cycles. With optimum full well clocking and three phases we get a gradient of <0.001 e- per line, i.e for a 2k chip <2e- spurious charge in the last row. We only used tri-level clocking for anti- blooming. The stronger effect is for sure the reduction of the positive upper rails, it looks like a factor of 3 every 1.5 V. Cheers, Ralf +--------------------------------------------------------------------+ | Ralf Kohley Tel.: +49 228 735658 | | Sternwarte der Universitaet Bonn Fax.: +49 228 733672 | | Auf dem Huegel 71 | | D-53121 Bonn | | Germany Email: rkohley@astro.uni-bonn.de | +--------------------------------------------------------------------+ From MYPIXEL at aol.com Tue Nov 11 10:49:37 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: ONE Message-ID: <971111094935_-1442324853@mrin47> ******** JJ here ******** In a message dated 97-11-10 10:45:20 EST, bburke@ll.mit.edu writes: << Yes, I'm on CCD-world. Like Gerry, I don't reply as much as I'd like. It's tough finding the time to read all my e-mail AND get my work done. ****** Thanks for the response .. yes, I can see one cannot respond to everything unless retired. ******** The low-noise output circuit that Gerry talks about is described in our recent paper "Soft-x-ray CCD imagers for AXAF" in the IEEE Trans. Electrons Devices, October 1997. This is a special issue devoted to Solid-State Image Sensors and full of interesting articles. For a new structure that promises even lower noise, you might look at "An epitaxially-grown charge modulation device" by my colleague Bob Reich in the same issue. ****** Will most definitely obtain these proceedings.. . I've heard about the modulation device and have a paper on it unread. ****** There is also some impressive work by Lester Kozlowski's group at the Rockwell Science Center that has led to sub-electron noise in silicon multiplixers coupled to IR detectors. I don't have the references handy, but keep an eye on this work. His techniques could have application to our visible imager devices. ****** Do you have Lester's e-mail .. . is he on CCD World? ***** Barry ******** Thanks again .. . Jim ******** From prj at ast.cam.ac.uk Tue Nov 11 10:38:47 1997 From: prj at ast.cam.ac.uk (Paul Jorden) Date: Thu Jul 29 11:54:24 2004 Subject: Position at MPAE CCD group (fwd) Message-ID: Hi everyone, I'm passing on this message from Uwe Keller (MPIA), who is about to join ccd-world... Regards, Paul J -------- Forwarded Message: From: Horst Uwe Keller Date: Tue, 11 Nov 1997 06:49:23 +0100 Subject: Position at MPAE CCD group To: PRJ@ast.cam.ac.uk Cc: sierks@pgate2.mpae.gwdg.de Dear Paul, I would like to come back to our phone conversation of last Friday. I would appreciate if you could dissaminate the attached job opening. We are looking for capable person in view of the long lasting involvement in the Rosetta mission and the upcomming change of generation. This could turn into a leading position depending on the qualification and commitment of the person. Thank you very much for your support. Uwe Keller Job opening at Max-Planck-Institute for Aeronomy (Germany) The Max-Planck-Institute for Aeronomy (MPAE) has been successfully involved in several space missions providing CCDs and readout electronics. Starting with the Giotto mission to comet Halley in the early eighties we provided CCDs for the Cassini and recently for Mars Pathfinder missions. Currently we are delivering cameras for further Mars landers and develop electronics for the science cameras of the Rosetta mission that will rendezvous with a comet in 2011. Here backside illuminated 2k by 2k CCDs will make state of the art imaging possible. We are looking for a colleague to strengthen our small CCD electronics group. We expect a person with experience in CCD testing and/or electronics development. Acquaintance with space electronics would be useful but is not required. The initial appointment is for 5 years. Depending on the qualification and personality a leading role within this group can be envisaged. Inquiries and applications to be addressed to: Dr. H. Uwe Keller Max-Planck-Institute for Aeronomy Max-Plack-Str. 2 37191 Katlenburg-Lindau Germany e-mail: keller@linmpi.mpg.de Tel.: +49 5556 979419 or +49 1715263274 Fax: +49 5556 979141 ------------------------------------------------------------------- Paul Jorden: prj@ast.cam.ac.uk Web: http://www.ast.cam.ac.uk/RGO Royal Greenwich Observatory, Madingley Road, Cambridge, CB3 0EZ, UK. Phone: +44 (0) 1223- 374000 \direct phone- 374811 \RGO Fax- 374700 From rreiss at eso.org Mon Nov 10 18:25:18 1997 From: rreiss at eso.org (Roland Reiss) Date: Thu Jul 29 11:54:24 2004 Subject: Output Amps Spice Models? Message-ID: <3467356E.9899271D@eso.org> I know this has been asked before: Are there any Spice models available for CCD output amplifiers? I'm currently looking into different pre-amplifier configurations and a model for the on-chip Fets would extremely helpful. Roland Reiss ESO From rkohley at astro.uni-bonn.de Mon Nov 10 17:33:14 1997 From: rkohley at astro.uni-bonn.de (Ralf Kohley) Date: Thu Jul 29 11:54:24 2004 Subject: Parallel clocking issues Message-ID: <9711101533.AA03262@aibn57.astro.uni-bonn.de> Hi Roger and all, we've experimented with finding an optimum setup for the parallel clocks, which is not that trivial and even slightly different from device to device of the same kind of CCD. I tried to summerize some effects in my SPIE 95 article (Vol. 2415). There are different kinds of full well limitation to be considered: example: thick Loral 2k x 2k, 15 um 1. Integration full well Do you operate in the bloomed or surface full well regime? a) Bloomed full well (less positive voltages in upper rail, say between 0 and 1.4 V): Blooming occurs before electrons reach the surface (Si-Si02 interface) ( < 200000 e- ) b) Surface full well (more positive voltages in upper rail, say between 1.4 and 6 V): Blooming occurs at very high values ( >>200000 e-), but electrons reach the surface much before. => residual images c) Optimum full well "intersection of surface and bloomed full well" Blooming occurs just at the moment when electrons reach the surface, noramlly the best ( 1.4 V leading to 200000 e- capacity ) 2. Transport full well (parallel clocks) Again, do you operate in the bloomed or surface full well regime? Normally during integration on a MPP-CCD, the additionally doped phase plays the role as the barrier (-8 V or whatever). During transport it also becomes a collecting potential, but the well is not as deep as for the other two phases. We found a difference of +2.5 V, which we use as an offset for this particular phase. I believe, that most full well limitation arise from transport rather then from integration. a) Bloomed full well Blooming occurs, but no smearing b) Surface full well No blooming, but smearing of a part of the charge due to bad CTE of charge transported along the surface. c) Optimum full well We reach optimum full well with P1: -8 V to +1.4 V P2: -8 V to +1.4 V P3: -5.5 V to +3.9 V 3. Transport full well (parallel transfer gate) Are the transfer gates in both directions equally doped? If not and you use a fixed voltage for the transfer gates, you can get different full wells in both directions. On inversion: I did a test with switching voltages between integration and read-out. Take a look at http://www.astro.uni-bonn.de/~rkohley/paper/eso96.html More on spurious charge: We don't use tri-level clocking during read-out, since the the production of spurious charge scales with clocking cycles. With optimum full well clocking and three phases we get a gradient of <0.001 e- per line, i.e for a 2k chip <2e- spurious charge in the last row. We only used tri-level clocking for anti- blooming. The stronger effect is for sure the reduction of the positive upper rails, it looks like a factor of 3 every 1.5 V. Cheers, Ralf +--------------------------------------------------------------------+ | Ralf Kohley Tel.: +49 228 735658 | | Sternwarte der Universitaet Bonn Fax.: +49 228 733672 | | Auf dem Huegel 71 | | D-53121 Bonn | | Germany Email: rkohley@astro.uni-bonn.de | +--------------------------------------------------------------------+ From MYPIXEL at aol.com Mon Nov 10 10:55:58 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: Super LDD Message-ID: <971110095557_1170007400@mrin84.mail.aol.com> Gerry, Some other inquiries about Lincoln amp if you don't mind. . . As mentioned in previous note. . . rumor has it that Lincoln spaces their Source and Drains a Buick distance away from output amplifier gate. This is great in lowering gate capacitance (i.e., Super LDD). However, series resistance of low doped material between would lower voltage gain significantly. I'm wondering do you know if they employ an additional mid dose implant (say arsenic) to lower resistance in this region? Also, what load resistance do you use these days? A single stage amplifier operating at 20 uV/e- does not have much transconductance. Therefore, any load you tie to it will lower on-chip gain. The 20 k load resistance is the most popular today (this hasn't changed for nearly 24 years !). I would think this would be too low for your purpose (any idea what your gate to source gain is when loaded?). Are you into constant current diodes for loads? Why not a dual stage amp . ? . . this would circumvent the load problem and give higher speed to the CCD. I'm assuming you are single stage. Any idea of what the amp channel doping is and drive temperature. . ? the trend has been to keep doping low (say 6e11) to maintain a low VDD. Channel drive times are kept to a minimum too (say 1050 for one hour). We appreciate your opinions and insight along these lines . . . Thanks much .. . jj From brucet at pcnet.com Mon Nov 10 10:33:53 1997 From: brucet at pcnet.com (Bruce Truax) Date: Thu Jul 29 11:54:24 2004 Subject: fits or img to ascii Message-ID: <199711101429.JAA08041@pcnet1.pcnet.com> >On Sun, 9 Nov 1997, David Waite wrote: > >> Does anyone know of a program that converts fits or img files to ascii so >> that I can export the camera data and analyse it using origin? Also, I am >> looking for software that allows me to do either vertical (1x512) or >> horizontal (512x1) binning. >> >> Thanks >> >> David Waite >> Institut fuer Experimentalphysik >> Freie Universitat Berlin >> Arnimallee 14 >> D-14195 Berlin >> Germany >> >> Phone +49.30.838.4776 Fax +49.30.838.5567 >> e-mail: waited@physik.fu-berlin.de >> If you have access to a Macintosh there is a shareware program called GraphicConverter which has the ability to handle a very wide wariety of graphic format conversions including FITS to ASCII. ____________________________________________________________ Bruce E. Truax Calypso Telescope Truax Associates email: brucet@pcnet.com 388 Wedgewood Road voice: 860-276-0450 Southington, CT 06489 fax: 860-620-9026 _____________________________________________________________ From bburke at ll.mit.edu Mon Nov 10 09:41:09 1997 From: bburke at ll.mit.edu (Barry E. Burke) Date: Thu Jul 29 11:54:24 2004 Subject: ONE In-Reply-To: <971109121141_-1509175958@mrin51.mail.aol.com> Message-ID: <9711100841.AA28753@LL.MIT.EDU> Dear Jim and CCD afficionados, >Guess I'll bug Barry. Is he on CCD World? Do you have his e-mail? . one >secret must be at the sense node and how to connect to it for high >sensitivity. I wish we could compare notes. > Yes, I'm on CCD-world. Like Gerry, I don't reply as much as I'd like. It's tough finding the time to read all my e-mail AND get my work done. The low-noise output circuit that Gerry talks about is described in our recent paper "Soft-x-ray CCD imagers for AXAF" in the IEEE Trans. Electrons Devices, October 1997. This is a special issue devoted to Solid-State Image Sensors and full of interesting articles. For a new structure that promises even lower noise, you might look at "An epitaxially-grown charge modulation device" by my colleague Bob Reich in the same issue. There is also some impressive work by Lester Kozlowski's group at the Rockwell Science Center that has led to sub-electron noise in silicon multiplixers coupled to IR detectors. I don't have the references handy, but keep an eye on this work. His techniques could have application to our visible imager devices. Barry From apo at ast.cam.ac.uk Mon Nov 10 10:13:27 1997 From: apo at ast.cam.ac.uk (Captain PeekHard) Date: Thu Jul 29 11:54:24 2004 Subject: fits or img to ascii References: Message-ID: <3466D037.5A4C@ast.cam.ac.uk> Hi David You can used a mime or uu encoder to convert ANY binary file to ASCII. Thats how most mailers do their attachments. The resulting file will be 2-3 times bigger and be readable as a plin text file. I can let you have more details if you cant find a free or shareware version of the programme Paddy -- THE RGO LIVES ON........................................| ...Surfing in CyberSpace on the Wings of a Storm... | _/_/_/ _/_/ _/_/_/ _/_/_/ _/ _/ | _/ _/ _/ _/ _/ _/ _/ _/ _/_/ | _/_/_/ _/_/_/ _/ _/ _/ _/ _/ | _/ _/ _/ _/ _/ _/ _/ _/ | _/ _/ _/_/_/_/_/ _/_/_/_/ _/ | | Contact::Tele +44 (0)1223 374836 | Fax +44 (0)1223 374700 | E-Mail apo@ast.cam.ac.uk | Web www.ast.cam.ac.uk/~apo/docs/ccds.html | --------------------------------------------------------/ From mahan at aurora.phys.utk.edu Sun Nov 9 17:45:15 1997 From: mahan at aurora.phys.utk.edu (Stephen L. Mahan) Date: Thu Jul 29 11:54:24 2004 Subject: fits or img to ascii In-Reply-To: Message-ID: David, Interactive Data Language (http://www.rsinc.com) when coupled with the IDL astronomy library (maintained by Wayne Landsman at the website: http://idlastro.gsfc.nasa.gov/homepage.html) works nicely for reading FITS files. Lets assume the image is 512x512 pixels, after read with a simple call to a read_fits function (either interactively or with a program you write), the array can be binned by summing subregions of the image- so if we wish to bin horizontally into a 1-D array (being the vertical binned img), we issue the command v_bin_variable=total(image_variable, 1) (where 1 is the dimension), if want to do a horizontal binning you can rotate the image or devise other strategies to do this). The result is a variable having the data, then one can save this array to an ascii, fits or a number of other formats. -Steve On Sun, 9 Nov 1997, David Waite wrote: > Does anyone know of a program that converts fits or img files to ascii so > that I can export the camera data and analyse it using origin? Also, I am > looking for software that allows me to do either vertical (1x512) or > horizontal (512x1) binning. > > Thanks > > David Waite > Institut fuer Experimentalphysik > Freie Universitat Berlin > Arnimallee 14 > D-14195 Berlin > Germany > > Phone +49.30.838.4776 Fax +49.30.838.5567 > e-mail: waited@physik.fu-berlin.de > __________________________________________________________________________ Stephen L. Mahan URL: http://aurora.phys.utk.edu/~mahan S&E 603 UT Complex Systems Lab Voice: 423-974-7850 Fax: 423-974-7843 Dept. of Physics & Astronomy, University of Tennessee Knoxville, TN 37996-1200 E-Mail: smahan@utk.edu __________________________________________________________________________ From waited at physik.fu-berlin.de Sun Nov 9 22:18:06 1997 From: waited at physik.fu-berlin.de (David Waite) Date: Thu Jul 29 11:54:24 2004 Subject: fits or img to ascii In-Reply-To: <971103133500_1346582197@mrin43.mail.aol.com> Message-ID: Does anyone know of a program that converts fits or img files to ascii so that I can export the camera data and analyse it using origin? Also, I am looking for software that allows me to do either vertical (1x512) or horizontal (512x1) binning. Thanks David Waite Institut fuer Experimentalphysik Freie Universitat Berlin Arnimallee 14 D-14195 Berlin Germany Phone +49.30.838.4776 Fax +49.30.838.5567 e-mail: waited@physik.fu-berlin.de From MYPIXEL at aol.com Sun Nov 9 13:11:42 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: ONE Message-ID: <971109121141_-1509175958@mrin51.mail.aol.com> ********* JJ here ****I**** In a message dated 97-11-07 00:16:41 EST, ger@hokupa.IFA.Hawaii.Edu writes: Hi Jim, Its great to see you on this forum. I don't reply as often as I should or would like, but I do read all the postings and your input will be great. ***** Thanks .. . I see what you mean by taking time to respond on CCD World. This is a great forum. Wish we had this service back when we distributing tens of thousands of CCD memos the old fashion way. ***** I too find the value of 0.96 e- at 20 kpix/sec to be amazing. That's why I'm careful not to hype the result, and I'w willing to make the X-ray data and other data I have available to anyone who wants to check it. ****** I guess 1.6 electrons to 1 electron isn't that much improvement over a 10 year period. Shows we are asymptotically approaching something physically. I wish I knew what that was . . . why 1 electron??? I've asked this question a thousand times. Could it be just coincidence. . . .? And it is 1 electron rms . . .something to do with quantum? When I saw that you calibrated with x-ray and photon transfer I knew in my heart it was real . . . . congratulations! If noise is still going down at 20 kpixels then the 1/f noise corner frequency must be very low (indicating good surface processing). Wouldn't be something to make a Lincoln Lab Skipper. . . 1 sample = 1 electron, 2 sample = 0.71 e-, 3 sample = 0.58, 4 sample = 0.5e-. Wouldn't do much good for extended objects or sky background (shot noise of one electron is 1 electron) . . . but for point and line sources the advantage would be there. ***** I wish I had all the numbers you'd like. We don't know the 1/f corner. The LL guys may, but they never test their amps at very slow rates and usually depend on us astronomers to do that for them. I can tell you the node sensitivity is huge -- 20 microvolts/e- or so. This is a big reason why we do as well as we do and why the effects from our downstream electronics are often negligible. We run our cameras with a vanilla Leach camera (with your old JPL preamp as the first stage). Operating temp is usually -90 to -110 for the various chips we've tested. ****** Wow . . . I've seen the good trend of getting sensitivity up with sacrifice of 1/f and white noise for many years. But I thought the trend was over. Guess sensitivity is winning out again. White noise must be pushing 20 nV/Hz with a sensitivity of 20 (the old WF/PC I CCDs exhibited 6 nV/Hz at 13 electrons noise at 0.4 uV/e for comparison . . when the sensitivity increase trend started). -110 is good for 1/f. That 1/f floor must be very good for a sensitivity like that. I had thought that high sensitivity implied higher 1/f noise. I think we have figured out where 1/f noise is coming from . . . at the source where drain current comes to the surface. Silvaco modeling shows that we don't stay buried at that point. If we moved LDD under the gate (which is not good for capacitance) it will stay buried and maybe 1/f goes away. The trick is to have both cases.' I understand that Lincoln has a large separation between gate and S/D (for depletion capacitive reasons). This is contrary to our measurements which show if the distance is too large series resistance eats up voltage gain (this occurs at about 2-microns). Do you know what Lincoln Lab uses? ******* When you measured the 1.7 e- noise way back when, you were probably using an old CCID-4 or a CCID-7. These typically had sensitivities in the range of 5-10 uvolts/e-. ****** We measured 4 -5 uV/e-. .. . see Fano Noise paper. ******* The LL amps have improved quite a bit since then (Barry Burke is always trying to do a bit better). On a CCID-10 we bottomed out at 1.7 e- as well. Then we received newer versions with improved sensitivity. These bottomed out at 1.2-1.4 e- noise (verified by Lick and AAO folks on the SAME CCD). When we designed our CCID20 (the 2Kx4K) we pushed LL to do even better and Barry tried a few more tricks. The node sensitivities are now more like 15-10 uvolts/e- and we have measured noise below 1.5 e- in many (more than 10) CCID-20s. We have only explored the noise "floor" on one device -- the one Richard Stover mentioned, device w78c1, posted on his web page. At the same pixel rate, our numbers agree. Our noise values are for thinned parts and frontside illuminated parts. We see no difference at the 1.5 e- level. I have not pushed a thinned part to see if it can get down to the 1 e- level. We are too busy screening the CCID20s as they pass through our lab and the lab at Lick. ******** At Pixel Vision/SITe we still see an average of 3 electrons (sample time of 8 micro-sec for 2 uV/e-). However, there is a considerable amount of Sandbox work going on to improve read noise and QE (we have lots defined up to Sandbox X). Everything else looks pretty good performance wise (but what else is there?). Guess I'll bug Barry. Is he on CCD World? Do you have his e-mail? . . . one secret must be at the sense node and how to connect to it for high sensitivity. I wish we could compare notes. Thanks for inputs . . . let me know if you have any more inputs to put on a Sandbox run. You got me going on the sensitivity.. . . I'll change some designs on the next run for sure. Great forum .. . . by the way, what you doing astronomy wise? Surf's up . . JJ ****** Aloha, Gerry From MYPIXEL at aol.com Sun Nov 9 13:11:29 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: More on Spurious Charge Message-ID: <971109121128_1548120426@mrin43.mail.aol.com> ***** JJ here ... . some responses below on sprurious charge .. . ***** Roger, Don't be sad. Nobody has the perfect CCD. Here at Lick we've tested many of the Lincoln 2Kx4K CCDs. They have superb noise performance as Gerry indicated. But like SITe they use a standard boron implant and they too have middling blue response. We expect Lincoln to switch to a two-layer AR coating which will help a lot but I think the spectacular blue response trophy will remain with Mike Lesser. **** A major CCD manufacturer needs to tranfer this technology into their processing lab. I might call Mike on that. . . **** Also, Lincoln CCDs are not MPP devices, and this makes life much more complicated. To keep spurious charge to a minimum we use parallel clock rails of +2 and -6. But this results is dreadful residual image for overexposed pixels. (Recall that the bulk of residual image charge resides in long-lived traps at the Si/SiO2 interface and is eliminated by inverting all clocks in MPP mode.) ****** I gather to keep the dark current down you need to keep pumping (clock) the Lincoln Lab CCD during integation (because of lack of MPP). Yes, what a spurious charge generator! Why Lincoln never went with MPP like everyone else is a real mystery. Recall RCA took over 10 years to replace their surface channel output amplifier to buried channel (and then it was too late . . . they closed down). We lived with 30 electrons noise during that time and all the other manufacturers raced by them. Stubborness gets you knowhere. For what it is worth. . . groups that want to eliminate residual image when operating non inverted . . . . . . place CCD into inversion for a short period of time before readout commences (1 line readout is all that is necessary). Charge in oxide will be swallowed by holes instantaneously eliminating surface residual image (SRI). For the rest of the readout you can operate noninverted (with dark current and full well sacrifice however). One can also pulse the substrate positively (we did this on WF/PC I) with all clocks low before integration. This forces the device into inversion eliminating SRI. These techniques will remove SRI ONLY for earlier images taken. To eliminate SRI during readout operate the CCD in the bloomed full well (BFW) mode. This will prevent charge from reaching the surface under bright lighting conditions. Recall from full well transfer that the user can either allow charge to reach surface or bloom or barrier phases. Optimum full well is when surface full well (SFW) =BFW. That is, when charge reaches the surface and blooms simultaneously. Tri-level clocking may be necessary for those difficult spurious charge situations (dont' recommend going to such a complicated clocking scheme unless it is absolutely necessary). Galileo has employed tri-level clocking (virtual phase CCD). The rising edge is the culprit for spurious. Start the clock moving slowly at first to let holes come out gracefully (sometimes a LC circuit is used for that purpose. . an RC is not optimum because slowness occurs at the end and not the beginning). Always limit the positive swing to SFW = BFW (unless clocked AB is used). Note . residual bulk image (RBI) is not influenced by inversion or full well conditions and sometimes gets included into SRI discussions. That's another story. JJ *********** Richard Stover UCO/Lick Observatory University of California Santa Cruz, CA 95064 USA Voice: 408-459-2139 FAX: 408-459-5244 FAX: 408-426-3115 (Alternate) email: richard@ucolick.org From MYPIXEL at aol.com Sun Nov 9 13:11:47 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: RCA Thinning Message-ID: <971109121146_1624824426@mrin58.mail.aol.com> ***** JJ here. .. Gary some questions below if you don't mind . . Thanks ****** >In a message dated 97-11-05 10:57:23 EST, ghughes@sarnoff.com writes: > > For many years Sarnoff has been using a CCD thinning process originally > developed in the late '70s for Si vidicons that does not require > pre-lapping or pre-thinning. While the details of this process are >propritery, it has several advantages over the thinning techniques used > for most astronomical grade CCDs: ****** Wasn't this the process described in the RCA Review in the 1970's when vidicon were being built? I've always been impressed with this process . . . and goes back to the Big CID (one the first commercial CCDs I measured in 1973 I think . . . to bad it was surface channel). ***** > * An electrically stable back surface is created that has excellent blue ****** Is this the process where you thin wafer, implant, anneal, deposit aluminum, mount on glass and dice? Again if it is I've always been impressed how you handle wafers during aluminum deposition without breaking them . .etc. ***** > and UV response. No flash gate or lumogen coating is required. ****** Can you tell me the QE (without AR) at 4000 A?. Should be 50 % when pinned. Implanted CCDs are coming in about 1/2. ******* > * It is a whole-wafer process (currently 4", scalable to 6"). ****** Are you going to 6-inch? ****** > * No etch-stop layer is required. Silicon thickness of 10-12 micron is > achieved routinely over the whole wafer. ***** That is interesting and different. Do you still mount glass to the back surface? ***** > * Bonding the thined whole wafer to a transparent substrate allows dicing > and packaging without exotic silicon bond-pad vias. ******** Guess that answers my question. But you can thin glass away if you want (for UV). > * Has reasonably low dark current without MPP (typically 200-500 pA/cm^2 at > 25C). ****** All thinned groups do report a high dark current like this even for MPP. Frontside MPP dark current normally ranges from 10 - 25 and sometimes less (Kodak is 3 at 300K). So there must be dark current coming from the backside indicating things aren't pinned. Flash gate, backside charging and MBE have shown lower dark current after thinning (which theory would predict). Why not MPP for you guys? ********* > * Provides high MTF (low point spread) with thick Si substrates (for high > red/near-IR Q.E.) while still being compatible with MPP operation for low > dark current. *********** So you are MPP? ********** > * No warping of completed chips. >> ****** Now that is a good advantage . . . what is your spec. ? Do you have any zebra effect due to glass mounting? ******* JJ .. . From MYPIXEL at aol.com Sun Nov 9 13:11:39 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:24 2004 Subject: NOISE BELIEVED Message-ID: <971109121138_716667498@mrin46.mail.aol.com> ********** JJ here . . . . ******* In a message dated 97-11-06 18:35:02 EST, richard@ucolick.org writes: Jim, Take a look at our Lincoln results at Lick: http://gardiner.ucolick.org:80/~ccdev/lincoln/lincoln.html Select W78C1 to see some of our early noise results. We didn't check at the long integration times used by Gerry Luppino, but the trend toward his value is clear. I think Gerry's value is believable. ********** Shows you how long I've been out of the loop . . . see my response to Gerry. You guys are doing some great CCD work . . Jim ********* From MYPIXEL at aol.com Sun Nov 9 13:11:32 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:25 2004 Subject: APS and Thinning Message-ID: <971109121131_630104554@mrin41.mail.aol.com> ******* JJ here ******** In a message dated 97-11-05 14:39:35 EST, ninkov@cis.rit.edu writes: Jim Janesick ... I use both back (SITe) and front (Kodak 4K x 4K) illuminated cooled CCDs in the lab here at RIT so I am always interested in knowing more about how they work. In addition we have designed and fabricated active pixel sensors (APS - for us this is two MOS capacitors per pixel for storage-sense + amplifier and two switches) devices using our campus microelectronics facility. For a variety of reasons (fill factor) we have been thinking about ways of fabricating back illuminated APS devices. ****** One of the benefits of APS is low cost (i.e., CMOS direct). Are you sure you want to get into thinning? Why not just stick with the expensive CCDs for high QE. Or are you looking towards mass production thinning (that would be exciting for the CCD too). Watch out when you loose your substrate to thinning. Most of our work these days at Pixel Vision focuses on achieving high speed for thinned CCDs (30 frame/sec rates). Amazing new things discovered on this front. Guess we will present a paper at SPIE (San Jose) on this. ***** My questions regarding back side surface roughness came up in talking with people in the Center for Optics Manufacturing in the Laboratory for Laser Energetics (DOE lab) here in Rochester. They have been working on a method for optical finishing called "magnetorheological finishing" (MRF). In MRF a magnetically-field-stiffened ribbon of fluid is used to polish out a workpiece. A spot of the stiffened fluid is swept across the surface of interest performing a sub-aperture lap. The standard fluid used is the carbonyl ion in water, although cerium oxide oxide is added for accelerated removal rates. Determinstic finishing is accomplished by mounting the part to be finished on a computer numerical controlled machine. The main interest of the group has been in the determinstic manufacturing of aspheric components. They quote, as an example, of starting with plano-convex aspheres (hyperboloids), 47 mm in diamter, with 140 microns of aspheric departure and a surface roughness of 1 micron rms. In a two step process requiring about a 140 minutes they removed material so as to have the form rms error reduced to 0.8 micron from that required for the desired asphere shape. The rms surface roughness measured was 10 Angstrom and no sub-surface damage was introduced (as judged by HF acid etching identical parts). The group has also investigated planarizing silicon wafers, evidently with good initial results. As an interested user, but non-CCD thinner, I have this maybe simplistic notion that the smoother the back surface of the CCD is after thinning the better it would be ? (i.e. passivation may not be as difficult). The rougher the surface is the more places there are for "bad" sites and traps to occur. The above MRF technique attracted my attention because of the amazingly small (at least to me, and much less than the micron you mentioned in your e-mail) surface roughness number, and the control they have on the final accuracy of the surface shape. Also the technique in initial tests has worked on silicon. ***** You are dealing in the devils world. Anything is possible. If surface roughness makes it easier to grow a good oxide (flash oxide) and accumulate then you are on to something. I haven't seen any evidence that roughness has a significant effect on either. But usually one thing leads to another when doing research in this area. Let us know if you need some pre-thinned CCDs for your experiments . . . JJ ***** More information on the MRF method is available in ; SPIE Critical Reviews of Optical Science and technology volume CR67, page 251 - Golini et al [1997] SPIE vol 3134 Jacobs et al [1997], and (for pretty pictures) Laser Focus World September 1995 , page 83 - Zoran -- Dr. Zoran Ninkov Center for Imaging Science Rochester Institute of Technology 54 Lomb Memorial Drive Rochester NY 14623-5604 tel : 716 - 475 7195 fax : 716 - 475 5988 e-mail : ninkov@cis.rit.edu >> From roger at ctios1.ctio.noao.edu Sat Nov 8 15:44:14 1997 From: roger at ctios1.ctio.noao.edu (roger smith x294) Date: Thu Jul 29 11:54:25 2004 Subject: Image ringing Message-ID: <9711081744.AA25677@ctios1> Gerry (Luppino), Richard (Stover), and Jim (Janesick): your replies on Lincoln CCDs and spurious charge were very interesting. Thanks Mark (Clampin), I appreciate this kind of input to ccd-world. More on line start transients.... [ This is pretty basic stuff but I think its always useful to have a complete catalog of CCD/controller phenomena. ] I have encountered another cause of line start transients in addition to the ground bounce that Mark described, i.e., droop/recoil of clock levels due to variation in current drawn from the serial clock drivers feeds through into the signal. During parallel shift, the serial clock drivers see no load current and thus recoil a little. During pixel skips before a Region of Interest or when skipping the serial register extension clocks to droop a little since the skips are faster than reads and the clock capacitance draws more average current. Properly designed drivers shouldn't ring much. Obviously the effects will vary with the clock driver characteristics and the amount of capacitive coupling between your clocks and the signal (primarily within the CCD). For cameras working at high speeds one uses stiffer clock buffers to get fast settling but one also has more stringent requirements. The variation in load current gets passed on to the supplies unless you have lots of local ballast caps, so you might also check that your problems don't originate with power supply distribution impedances and/or insufficient bypassing, etc. A word of caution for anyone looking for these effects with a scope....you are looking for a small variation in a large clock swing. We can easily see transients at a level a few electrons on a low noise CCD, and even less when line averaging. Whether this level matters is another issue. This is only a few (tens of) microvolts at the CCD output. If you see a typical serial clock feed-through of 100 mV or so for a 10 V swing, this means that 1% of serial clock fluctuations will propagate to the signal. Your Double Correlated Sampler measures the slope of the clock amplitude change so there as another safety margin. However, depending on the details you might only be looking for a 0.1-1% variation of a ten volt serial clock swing, not something that leaps out at you! I get rid of the last vestiges of the transient by expanding the region to be read by about 10 pixels and then trimming these off automatically in the image processing. This only works if you have a CCD with 10 or more pixels of serial register extension of course, and for regions of interest. The readout time over head for most astronomers is negligible since they are generally reading many more than 10 pixels per line. We do the same kind of trimming at the start of the overscan since a transient can appear there when there are fast pixel skips between the region of interest and its corresponding overscan. In theory, one can calibrate the effect out but then one has to question how stable the effect is. Roger From roger at ctios1.ctio.noao.edu Thu Nov 6 20:25:39 1997 From: roger at ctios1.ctio.noao.edu (roger smith x294) Date: Thu Jul 29 11:54:25 2004 Subject: Parallel clocking issues Message-ID: <9711062225.AA15950@ctios1> Richard, That was a very informative and interesting response. Lincoln CCDs seem a lot less mythical now that I have heard some of the caveats. I;ve had some success controllign spurious charge by simply reducing the high level of the parallel clocks. Everyone, I feel that we still have a lot to learn about optimizing parallel clocking and would welcome contributions. Between us we may know most of the answers but I don't know where to find a review article or text that brings together a description of all the issues and funny effects. Does anyone else? Here are a couple of my own observations/comments.... 1) Spurious charge reduction: I'm surprised how much spurious charge generation I often see: 2-4 e- from 2K SITe CCDs read through one side, MPP, typically using -7.5 to +3V clocks (non-barrier phase) with 120 us rise times (10%-90%) and ~ 1ms period, and similar numbers for Teks and Lorals. I have experimented very little with rise time since it is fiddly to change and is already very slow. I find that the going more negative on the low rail increases the spurious charge only slightly, but that less positive upper rails have a strong effect on reducing spurious charge. It also reduces well capacity at a similar rate but those needing low spurious charge are worried about noise and not so much about bright limits. Maybe the folks who have done tri-level clocking can venture an explanation. Are you there Ralf Kohley? 2a) Full well dependence on direction! 2b) How much clock crosstalk is acceptable? Am I the only one on this planet who gets different full well when clocking downwards compared to upwards?! Scoping the clock signals where they enter the dewar reveals similar looking waveforms for each clocking direction. However the details of the crosstalk (0.5 to 1V) due to inter-electrode capacitance, may differ subtly. My hunch is that this holds the secret, but I haven't worked out the theoretical details or proven this to be the case by changing the crosstalk. I can do this by changing the outpu impedance and edge rates of the clock drivers. 3) I sometimes see spurious charge vary with clocking direction too. 4) I expect spurious charge to be flat and it usually is, since every line has been clocked all the way from the opposite edge either during the erase prior to the exposure or during the readout. However I sometimes see an increase with distance from the readout amp. One possibility is that the parallel clocks don't settle completely during fast erase (continuous parallel shifting) so that they have lower amplitude than during readout and thus incur less spurious charge. 5) What's the easiest way to confirm the negative level that induces inversion? I tried the suggestion (by Morley Blouke) to measure dark current as a function of parallel clock low voltage, at an elevated temperature so that dark measurements could be made rapidly. It works beautifully. I havn't repeat this at low temperature to show that the threshold is invariant with temperature since it will take days to do. 6) For CCDs with an MPP implant, should the barrier phase be set the same as he other phases or offset positive? If so, how do you determine by how much? At last year's Garching conference I asked this question to various CCD manufacturers and pundits and got conflicting answers. The above test, shows clearly that the dark current versus "clock low voltage" curve is offset several volts positive for the barrier phase. Before making a choice though, one should look at how spurious charge and full well vary too. 7) How do you explain *serial* smearing of bloomed pixels given that the serial register has greater capacity than the image pixels? (This CCD has a barrier implant under Transfer Gate.) The serial trail doesn't start for 10-20 pixels after the bloomed columns, and neighbouring columns don't always exhibit the same behavior when similarly illuminated. Roger From ger at hokupa.IFA.Hawaii.Edu Thu Nov 6 15:06:27 1997 From: ger at hokupa.IFA.Hawaii.Edu (Gerard Luppino) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious charge in low noise CCDs? Message-ID: <199711070006.OAA10725@hokupa.ifa.hawaii.edu> Hi Jim, Its great to see you on this forum. I don't reply as often as I should or would like, but I do read all the postings and your input will be great. I too find the value of 0.96 e- at 20 kpix/sec to be amazing. That's why I'm careful not to hype the result, and I'w willing to make the X-ray data and other data I have available to anyone who wants to check it. I wish I had all the numbers you'd like. We don't know the 1/f corner. The LL guys may, but they never test their amps at very slow rates and usually depend on us astronomers to do that for them. I can tell you the node sensitivity is huge -- 20 microvolts/e- or so. This is a big reason why we do as well as we do and why the effects from our downstream electronics are often negligible. We run our cameras with a vanilla Leach camera (with your old JPL preamp as the first stage). Operating temp is usually -90 to -110 for the various chips we've tested. When you measured the 1.7 e- noise way back when, you were probably using an old CCID-4 or a CCID-7. These typically had sensitivities in the range of 5-10 uvolts/e-. The LL amps have improved quite a bit since then (Barry Burke is always trying to do a bit better). On a CCID-10 we bottomed out at 1.7 e- as well. Then we received newer versions with improved sensitivity. These bottomed out at 1.2-1.4 e- noise (verified by Lick and AAO folks on the SAME CCD). When we designed our CCID20 (the 2Kx4K) we pushed LL to do even better and Barry tried a few more tricks. The node sensitivities are now more like 15-10 uvolts/e- and we have measured noise below 1.5 e- in many (more than 10) CCID-20s. We have only explored the noise "floor" on one device -- the one Richard Stover mentioned, device w78c1, posted on his web page. At the same pixel rate, our numbers agree. Our noise values are for thinned parts and frontside illuminated parts. We see no difference at the 1.5 e- level. I have not pushed a thinned part to see if it can get down to the 1 e- level. We are too busy screening the CCID20s as they pass through our lab and the lab at Lick. Aloha, Gerry From richard at ucolick.org Thu Nov 6 14:51:34 1997 From: richard at ucolick.org (Richard Stover) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious charge in low noise CCDs? In-Reply-To: <3c864d97.34622886@aol.com> Message-ID: Jim, Take a look at our Lincoln results at Lick: http://gardiner.ucolick.org:80/~ccdev/lincoln/lincoln.html Select W78C1 to see some of our early noise results. We didn't check at the long integration times used by Gerry Luppino, but the trend toward his value is clear. I think Gerry's value is believable. >>In a message dated 97-11-06 05:14:50 EST, ger@hokupa.IFA.Hawaii.Edu writes: >> >><< The record we have achieved so far is 0.96 e- noise at 20 kpixels/sec. >> >> >> >>Sorry Gerry . .. this is hard to believe. But you can help me out. What is Richard Stover UCO/Lick Observatory University of California Santa Cruz, CA 95064 USA Voice: 408-459-2139 FAX: 408-459-5244 FAX: 408-426-3115 (Alternate) email: richard@ucolick.org From MYPIXEL at aol.com Thu Nov 6 16:33:31 1997 From: MYPIXEL at aol.com (MY PIXEL) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious charge in low noise CCDs? Message-ID: <5988b999.3462296c@aol.com> In a message dated 97-11-06 05:14:50 EST, ger@hokupa.IFA.Hawaii.Edu writes: We are trying our best to get these devices out into the hands of the public -- so to speak. It is wonderful that EEV are now able to produce quite low noise amps as well. I think we just have to keep pushing on all the manufacturers. ********* If we are sincere you can help by unveiling the secrets .. . . . . Jim How are you doing Gerry? ****** From MYPIXEL at aol.com Thu Nov 6 16:29:41 1997 From: MYPIXEL at aol.com (MY PIXEL) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious charge in low noise CCDs? Message-ID: <3c864d97.34622886@aol.com> In a message dated 97-11-06 05:14:50 EST, ger@hokupa.IFA.Hawaii.Edu writes: << The record we have achieved so far is 0.96 e- noise at 20 kpixels/sec. >> Sorry Gerry . .. this is hard to believe. But you can help me out. What is your 1/f corner frequency at operating temperature (in Hertz), your white floor (in V per root Hertz) and node sensitivity (Volts/electron), and your system bandwidth? From there we calculate . . . . On the other hand . . . I do recall measuring 1.7 electrons ten years ago for Lincoln. Need a second opinion . . .? Jim From MYPIXEL at aol.com Thu Nov 6 16:21:47 1997 From: MYPIXEL at aol.com (MY PIXEL) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious . .. friend or foe? Message-ID: <9a073ce4.346226ad@aol.com> In a message dated 97-11-06 04:57:18 EST, roger@ctios1.ctio.noao.edu writes: Jim Janesick here . . . << To those fortunate enough to have access to CCDs with high output sensitivity (>5uV/e-).... 1. Does the very low read noise that you report (e.g. for EEV or Lincoln Labs CCDs) include spurious charge injection ? **** I'm sure they assume none. To date I have not heard of any group that can''t control spurious charge to zero. This goes back 17 years when spurious charge was invented (when we inverted the CCD). Clock waveshaping or tri-level clocking are the two main solutions. Galileo uses tri-level. It had to . . . unchecked spurious saturated the CCD (this is a virtual phase for you)! We like the vertical registers to be inverted (friend). Normally the horizontals are not inverted for spurious reasons. Are you having spurious problems? **** 2. How much spurious charge injection is there (with clock levels chosen for good full well, and rise times to support the impressive read rates also quoted) ? **** Very complex question. Spurious is a function of everything (even operating temp . . . it increases when going cold). It is very diffcult to compare spurious questions and answers with others. The best way to comunicate is say there is none. ***** Sad isn't it, that low noise outputs have been around for 7 years and we are only now seeing the first few commercial devices trickle out. The national observatories don't have a single spectrograph equipped with a CCD that has the combination of state art QE and noise. We have SITe/Tek chips with middling blue response and 2.5-3 e- noise, or Lesser/Loral CCDs with excellent blue response but 6-7 e- noise. Although everyone is building mosaics we still desperately need better spectroscopic CCDs. Suggestions welcome! ***** You hit the nail on the head .. . about having everything one chip. .. . very old problem. But on the other hand we have seen the edge of the universe (did it make a difference?). I'm sure your note will prompt some advertizement from CCD manufacturers (by the way, how about a Pixel Vision CCD? . . . just kidding) ****** Roger Smith, National Optical Astronomy Observatories. >> From richard at ucolick.org Thu Nov 6 12:40:17 1997 From: richard at ucolick.org (Richard Stover) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious charge in low noise CCDs? In-Reply-To: <9711060208.AA11326@ctios1> Message-ID: Roger, Don't be sad. Nobody has the perfect CCD. Here at Lick we've tested many of the Lincoln 2Kx4K CCDs. They have superb noise performance as Gerry indicated. But like SITe they use a standard boron implant and they too have middling blue response. We expect Lincoln to switch to a two-layer AR coating which will help a lot but I think the spectacular blue response trophy will remain with Mike Lesser. Also, Lincoln CCDs are not MPP devices, and this makes life much more complicated. To keep spurious charge to a minimum we use parallel clock rails of +2 and -6. But this results is dreadful residual image for overexposed pixels. (Recall that the bulk of residual image charge resides in long-lived traps at the Si/SiO2 interface and is eliminated by inverting all clocks in MPP mode.) So we are experimenting with erase-clocking which will drop all parallel clocks to a sufficiently negative level to erase the residual image. We haven't figured out yet the best way to do this. Also we find that we can get an amazingly high pixel full well of something like 400Ke- if we use parallel clocks of +4 and -6. (This is much more charge than the high gain on-chip amplifier can handle, but the large full well is still useful to minimize blooming.) We might even want to go to +4 and -8 to get partial inversion and lower dark. But if we do this we'll need to come out of inversion slowly to limit spurious charge generation (which happens on the rising edge of the parallel clocks). So we think we may need one set of rails for integration, one or two sets for erasing, and another one for readout. The high resistivity Lincoln 2Kx4K CCDs may add an additional constraint on the parallel clocks to achieve full depletion and minimum lateral spreading - but we haven't begun to worry about that! It's going to take us some time to figure out how to operate these CCDs at their optimum. Another issue I haven't looked at yet is whether or not the controller Keck will be using (the SDSU Gen II) with these CCDs can easily produce all of these voltages when they are needed. One final plug - the high resistivity CCDs being produced at LBL may achieve excellent blue response, excellent red response, no fringing, large full-well, and all without thinning or difficult backside treatments. I hope to have some positive news at the Kona meeting. Richard Stover UCO/Lick Observatory University of California Santa Cruz, CA 95064 USA Voice: 408-459-2139 FAX: 408-459-5244 FAX: 408-426-3115 (Alternate) email: richard@ucolick.org From MYPIXEL at aol.com Thu Nov 6 15:32:52 1997 From: MYPIXEL at aol.com (MY PIXEL) Date: Thu Jul 29 11:54:25 2004 Subject: Image Ringing Message-ID: <49b7a683.34621b35@aol.com> Jim, You said in your reply last week that we were seeing ringing in the image at the beginning of each line readout. This is the problem I was referring to and would appreciate any comments on how we can remedy this situation. We are losing all of our leading overscan. To answer your question the image is a CTE frame, hence the bright points. Many thanks Mark Clampin >> Mark, We have experienced this problem on nearly every flight CCD camera built at JPL. . . Space Telescope, Cassini, Galileo, etc.. It is often seen in most ground based CCD cameras to some degree. . . . especially high speed ones. The first thing to consider is grounding. An impedance of a few ohms in series with the CCD ground will jerk the substrate substantially when the vertical clocks go off (the substrate current density is very high during this time). When the substrate voltage jumps your amplifier jumps with it, and in turn, introduces a transient in the signal processor at the beginning of each line. Take a look at your substate connection to the CCD. Make sure it isn't bouncing around. Your ground wire should show a few ohms AC wise .. . if not a big cap on the ground near the CCD should help. With good external grounding in place we then need to consider internal CCD grounding. Curiously CCD ground problems are often associated with the packaging of the CCD. For example, the epoxy used to glue the CCD down can exhibit an impedance (this was Cassini's problem in spades). However, you have a thinned CCD and other problems to worry about. You probably get your ground to the CCD through the substrate contacts. These contacts exhibit a fairly high impedance (> 10 ohms) and are not good grounds. In fact we recently eliminated the substrate contacts from our thinned Pixel Vision / SITe Sandbox high speed CCDs for that very reason. Instead we get our ground on the backside of the CCD (a little secret). This offers a low-impedance ground path for the holes that MUST come in and out of the CCD (taking the CCD out of inversion will alleviate the problem you have by reducing hole current required by inversion). We could say much more about grounding, however, chances are you can't do much about your grounds because the device and grounds are probably "fixed" in your system at this time. One solution is to give sufficient settling time between the vertical shift and when horizontal registers start up. Can you do this.. ? it is the easiest solution. However, your frame time will increase proportionally. The other solution is to look at your capacitors in your signal chain (the ones that AC couple your signal). They all have a certain time constant and are responsible for the spatial signature you see in your image. Make these time constants either as short as possible or long as possible (ideally the CDS should be DC coupled throughout to eliminate problems like this). This will change the time constant seen in your image (pick the direction you want to go). Let me stop here for futher questions if you have them . .. Good luck . . JJ PS .. . I would like to share this with CCD World if you don't mind . . . this problem is very common and people keep asking about it. From ger at hokupa.IFA.Hawaii.Edu Wed Nov 5 17:46:09 1997 From: ger at hokupa.IFA.Hawaii.Edu (Gerard Luppino) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious charge in low noise CCDs? Message-ID: <199711060246.QAA09771@hokupa.ifa.hawaii.edu> Hi Roger, When we quote noise values for our Lincoln CCDs, we quote the number measured on the output image from the device. We do not "correct" for system noise, or spurious charge and we do not take the difference of two images and divide by root 2. So the value quoted includes all the additional noise sources if present. The record we have achieved so far is 0.96 e- noise at 20 kpixels/sec. This is x-ray and light transfer curve calibrated gain and anyone is welcome to the data to verify. The same chip had similar noise measured by Lick and ESO with different chips and systems (and at slightly higher speeds, so their values were not quite as low). We have not really pushed the high speed end -- Jim Beletic is doing that. We have no intention of going as slowly as 20 kpixels/s, but we did want to see where the noise would "bottom out." We are trying our best to get these devices out into the hands of the public -- so to speak. It is wonderful that EEV are now able to produce quite low noise amps as well. I think we just have to keep pushing on all the manufacturers. Aloha, Gerry From roger at ctios1.ctio.noao.edu Thu Nov 6 00:08:08 1997 From: roger at ctios1.ctio.noao.edu (roger smith x294) Date: Thu Jul 29 11:54:25 2004 Subject: Spurious charge in low noise CCDs? Message-ID: <9711060208.AA11326@ctios1> To those fortunate enough to have access to CCDs with high output sensitivity (>5uV/e-).... 1. Does the very low read noise that you report (e.g. for EEV or Lincoln Labs CCDs) include spurious charge injection ? 2. How much spurious charge injection is there (with clock levels chosen for good full well, and rise times to support the impressive read rates also quoted) ? Sad isn't it, that low noise outputs have been around for 7 years and we are only now seeing the first few commercial devices trickle out. The national observatories don't have a single spectrograph equipped with a CCD that has the combination of state art QE and noise. We have SITe/Tek chips with middling blue response and 2.5-3 e- noise, or Lesser/Loral CCDs with excellent blue response but 6-7 e- noise. Although everyone is building mosaics we still desperately need better spectroscopic CCDs. Suggestions welcome! Roger Smith, National Optical Astronomy Observatories. From ninkov at cis.rit.edu Wed Nov 5 15:36:27 1997 From: ninkov at cis.rit.edu (Zoran Ninkov) Date: Thu Jul 29 11:54:25 2004 Subject: CCD Question References: <971104233826_1724806221@mrin46.mail.aol.com> Message-ID: <3460CABB.10D7@cis.rit.edu> Jim Janesick ... I use both back (SITe) and front (Kodak 4K x 4K) illuminated cooled CCDs in the lab here at RIT so I am always interested in knowing more about how they work. In addition we have designed and fabricated active pixel sensors (APS - for us this is two MOS capacitors per pixel for storage-sense + amplifier and two switches) devices using our campus microelectronics facility. For a variety of reasons (fill factor) we have been thinking about ways of fabricating back illuminated APS devices. My questions regarding back side surface roughness came up in talking with people in the Center for Optics Manufacturing in the Laboratory for Laser Energetics (DOE lab) here in Rochester. They have been working on a method for optical finishing called "magnetorheological finishing" (MRF). In MRF a magnetically-field-stiffened ribbon of fluid is used to polish out a workpiece. A spot of the stiffened fluid is swept across the surface of interest performing a sub-aperture lap. The standard fluid used is the carbonyl ion in water, although cerium oxide oxide is added for accelerated removal rates. Determinstic finishing is accomplished by mounting the part to be finished on a computer numerical controlled machine. The main interest of the group has been in the determinstic manufacturing of aspheric components. They quote, as an example, of starting with plano-convex aspheres (hyperboloids), 47 mm in diamter, with 140 microns of aspheric departure and a surface roughness of 1 micron rms. In a two step process requiring about a 140 minutes they removed material so as to have the form rms error reduced to 0.8 micron from that required for the desired asphere shape. The rms surface roughness measured was 10 Angstrom and no sub-surface damage was introduced (as judged by HF acid etching identical parts). The group has also investigated planarizing silicon wafers, evidently with good initial results. As an interested user, but non-CCD thinner, I have this maybe simplistic notion that the smoother the back surface of the CCD is after thinning the better it would be ? (i.e. passivation may not be as difficult). The rougher the surface is the more places there are for "bad" sites and traps to occur. The above MRF technique attracted my attention because of the amazingly small (at least to me, and much less than the micron you mentioned in your e-mail) surface roughness number, and the control they have on the final accuracy of the surface shape. Also the technique in initial tests has worked on silicon. More information on the MRF method is available in ; SPIE Critical Reviews of Optical Science and technology volume CR67, page 251 - Golini et al [1997] SPIE vol 3134 Jacobs et al [1997], and (for pretty pictures) Laser Focus World September 1995 , page 83 - Zoran -- Dr. Zoran Ninkov Center for Imaging Science Rochester Institute of Technology 54 Lomb Memorial Drive Rochester NY 14623-5604 tel : 716 - 475 7195 fax : 716 - 475 5988 e-mail : ninkov@cis.rit.edu From ghughes at sarnoff.com Wed Nov 5 11:57:35 1997 From: ghughes at sarnoff.com (GARY HUGHES) Date: Thu Jul 29 11:54:25 2004 Subject: Thinning Options In-Reply-To: Message-ID: <3.0.3.32.19971105105735.0070845c@postoffice.sarnoff.com> There is more than one way to thin a wafer. For many years Sarnoff has been using a CCD thinning process originally developed in the late '70s for Si vidicons that does not require pre-lapping or pre-thinning. While the details of this process are proprietary, it has several advantages over the thinning techniques used for most astronomical grade CCDs: * An electrically stable back surface is created that has excellent blue and UV response. No flash gate or lumogen coating is required. * It is a whole-wafer process (currently 4", scalable to 6"). * No etch-stop layer is required. Silicon thickness of 10-12 micron is achieved routinely over the whole wafer. * Bonding the thined whole wafer to a transparent substrate allows dicing and packaging without exotic silicon bond-pad vias. * Has reasonably low dark current without MPP (typically 200-500 pA/cm^2 at 25C). * Provides high MTF (low point spread) with thick Si substrates (for high red/near-IR Q.E.) while still being compatible with MPP operation for low dark current. * No warping of completed chips. At 04:50 AM 11/5/97 -0500, you wrote: >Mail*Link? SMTP RE>CCD Question > >In a message dated 97-11-04 18:15:35 EST, ninkov@cis.rit.edu writes: ><< > > As I understand it when CCDs are thinned for backside illumination > purposes the wafers are initially lapped to some intermediate thickness > >***** >Yes, sometimes mechanically and sometimes chemically >***** > > and then etched to the final desired thickness, which depends on the > wavelength of operation. > >****** >Ideally very near the frontside depletion edge but no more than a couple >microns from it. >****** > > Normally the etch stops (or at least slows > down significantly) at the interface between the epitaxial and substrate > silicon. > >***** >By about a factor of 100 >***** > > After this etching is concluded (and before backside damage > control is done) > >**** >you mean accumulation (i.e., surface passivation) right? >********* > >what is the rms surface roughness of the back surface? > >**** >This is sometimes called the orange peel (surface under micro-scope looks >like an orange skin). Less than a micron. . . >******* > > Is that figure larger if you stop at the epi-bulk boundary or if you > continue even thinner into the epi ? > >**** >good question . . you can't go much beyond the auto substrate doping region >(which is several microns thick typcially) or the global flatness degrades >which is a bigger concern (regions will thin faster than others because of >eddies). > >As far as the orange peel variance I would think it would be the same. >However, this question should be directed to Pauline at SITe who has about 15 >years thinning CCDs. Pauline. . . what do you think? > >Jim Janesick > >PS. why do you ask this question .. . are you thinning CCDs? > >****** > Thanks ... > > Zoran >> Regards, Gary Hughes Sarnoff Corporation 609/734-3056 609/734-2565 (fax) From MYPIXEL at aol.com Wed Nov 5 05:23:51 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:25 2004 Subject: CCD Question Message-ID: <971104233826_1724806221@mrin46.mail.aol.com> In a message dated 97-11-04 18:15:35 EST, ninkov@cis.rit.edu writes: << As I understand it when CCDs are thinned for backside illumination purposes the wafers are initially lapped to some intermediate thickness ***** Yes, sometimes mechanically and sometimes chemically ***** and then etched to the final desired thickness, which depends on the wavelength of operation. ****** Ideally very near the frontside depletion edge but no more than a couple microns from it. ****** Normally the etch stops (or at least slows down significantly) at the interface between the epitaxial and substrate silicon. ***** By about a factor of 100 ***** After this etching is concluded (and before backside damage control is done) **** you mean accumulation (i.e., surface passivation) right? ********* what is the rms surface roughness of the back surface? **** This is sometimes called the orange peel (surface under micro-scope looks like an orange skin). Less than a micron. . . ******* Is that figure larger if you stop at the epi-bulk boundary or if you continue even thinner into the epi ? **** good question . . you can't go much beyond the auto substrate doping region (which is several microns thick typcially) or the global flatness degrades which is a bigger concern (regions will thin faster than others because of eddies). As far as the orange peel variance I would think it would be the same. However, this question should be directed to Pauline at SITe who has about 15 years thinning CCDs. Pauline. . . what do you think? Jim Janesick PS. why do you ask this question .. . are you thinning CCDs? ****** Thanks ... Zoran >> From ninkov at cis.rit.edu Tue Nov 4 15:45:39 1997 From: ninkov at cis.rit.edu (Zoran Ninkov) Date: Thu Jul 29 11:54:25 2004 Subject: CCD Question References: <1116d9e1.345ec6a2@aol.com> Message-ID: <345F7B62.78E4@cis.rit.edu> As I understand it when CCDs are thinned for backside illumination purposes the wafers are initially lapped to some intermediate thickness and then etched to the final desired thickness, which depends on the wavelength of operation. Normally the etch stops (or at least slows down significantly) at the interface between the epitaxial and substrate silicon. After this etching is concluded (and before backside damage control is done) what is the rms surface roughness of the back surface. Is that figure larger if you stop at the epi-bulk boundary or if you continue even thinner into the epi ? Thanks ... Zoran -- Dr. Zoran Ninkov Center for Imaging Science Rochester Institute of Technology 54 Lomb Memorial Drive Rochester NY 14623-5604 tel : 716 - 475 7195 fax : 716 - 475 5988 e-mail : ninkov@cis.rit.edu From MYPIXEL at aol.com Tue Nov 4 02:55:12 1997 From: MYPIXEL at aol.com (MY PIXEL) Date: Thu Jul 29 11:54:25 2004 Subject: Another book! No 1998 workshop - next in 1999 Message-ID: <1116d9e1.345ec6a2@aol.com> In a message dated 97-11-04 01:32:08 EST, geary@cfa.harvard.edu (John Geary) writes: << How about a permanently rotating 3-year schedule of ESO, Cayman, and Kona conferences? Sounds good to me. --J. Geary >> How about Surf City . . . .? jj From MYPIXEL at aol.com Mon Nov 3 16:03:32 1997 From: MYPIXEL at aol.com (MYPIXEL@aol.com) Date: Thu Jul 29 11:54:26 2004 Subject: Noise Message-ID: <971103133500_1346582197@mrin43.mail.aol.com> Paddy, Attached find a short note to Jim B. about noise things in response to his EEV report (which was impressive). Yes, I heard at Cayman the 1.6 electrons for EEV.. . 0.1 electrons better than a Lincoln lab noise figure advertized 7 years before (backed up with photon transfer and x-ray). I can honestly say that Lincoln had a true noise figure back then. However, the CCD was at -100 C, employed 8 micro-sec sample timing, used an optimized load resistance and bias voltages were carefully set. We spent several weeks obtaining this noise level. I would guess that similar efforts would be required for any CCD assuming the raw on-chip amplifier performance was worth the effort. But where is the practical value? What group has the time to do this? I wish CCD manufactures would advertize average noise and stop with all the impression with the lowest value. Seems to me several groups are at the the 3 electron floor on the average. Below this comes with hard work from the user. As the world turns . . Jim Jim Beletic . . . see my note below. . . Jim Janesick Subj: Noise/speed performance of EEV CCDs Date: 97-11-01 09:38:24 EST From: jbeletic@eso.org (James Beletic) To: ccd-world@cfht.hawaii.edu I thought it was time to update you on ESO's work with EEV CCDs. As you may know, ESO has a contract with EEV for 20 scientific grade 2k x 4k CCDs with 15 micron pixel pitch. This is the so-called CCD44-80 as opposed to the CCD 42-80, which is the 13.5 micron pixel device being received by RGO et al. We are beginning to receive the 2k x 4k, 15 micron devices and we have some noise figures from the first frontside engineering grade device. We have hooked the CCD up to our new FIERA controller and measured the combined noise for CCD plus system. The figures we have obtained thus far (when we read two ports in parallel) are: 100,000 pixels/sec/port 2.8 electrons noise 500,000 4.3 1,000,000 6 to 8 Full frame readout using 2 ports at 1 million pixels/sec/port is completed in 4.3 seconds. With 2 x 2 binning, total readout time is 1.3 seconds. Note that these figures were obtained with clamp-and-sample circuitry and thus we are most likely a square root of 2 worse than the best noise possible with dual-slope CDS. During the 1996 ESO CCD workshop we stated that we are going to try to recover the square root of 2 by oversampling and post-processing the multiple samples per pixel. (Note this is different than the "skipper" approach - we plan a single move of charge to the output gate combined with multiple samples with the A/D converter.) We will soon be testing this approach and plan to report on it at the Kona conference (March 1998). If this approach is successful, we will use a DSP that is already built into the FIERA system to do the post-processing in real-time. If we are not successful with the oversampling approach, our backup plan is to use a dual-slope video board in those situations where the lowest noise is absolutely required (e.g. spectrographs). We do not have other figures to report at this time (e.g. CTE, etc.) but are pleased that the total noise of the CCD/system is good enough for us to complete putting together the 4k x 4k and 8k x 8k systems for direct sky imaging that will start operation on La Silla in 1998. Since the sky background will be very high for most images, we expect that many users will take advantage of the 1 million pixel readout rate. For the 8k x 8k, we plan to use only 1 port per CCD, but still expect to get full frame readout in 10 seconds or less. With best regards, Jim Beletic ========================================================================= James W. Beletic E-mail: jbeletic@eso.org European Southern Observatory Phone: +49-89-320-06520 Karl-Sch-Str 2, D-85748 Garching, GER FAX: +49-89-320-2362 ========================================================================= Hey Jim how are you doing. . . (looks like you are pretty busy from below)? Who would of guessed that a square-root of two wouldbe so important. I'd be interested in the "noise correlated" approach you will be trying and the mathematics that goes with it (i.e., multiple sampling as the video is falling). Most noise is correlated so don't expect to see a square-root with the number of samples taken. . . intuitively one might get a square-root of two for an infinite sample set. The double-sample-difference CDS technique does increase the white noise by the square-root of two. One might consider sampling the reference level at a smaller bandwidth to circumvent white noise in quadrature problem with the video sample. Also a multiple pole filter would decrease noise (we use a single pole) picking up a square-root-of two. Why don't you like Skipper .. .? for weak spectroscopic lines . . . wouldn't you like subelectron? We will be doing some Skipper work at Pixel Vision using very narrow channels under the floating gate (strickly low-signal level processing).