CCD-world: Re: Optimum CCD Set-up, from Mingzhi Wei

[MYPIXEL at aol.com]

Posted to CCD-world:
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In a message dated 97-11-25 23:43:35 EST, tmca at cfht.hawaii.edu writes:

<
 Hi Jim,

 Thank you very much for your comments. They are very helpful.

 Followings are my more comments.

 Mingzhi

*******jj
Here are some comments back . . . Jim Janesick
*******jj

 
 -----
 These measurements are done with very wide(300us) and long rising
time(100us)
 vertical clocks
 Mingzhi
 -----

******jj
I gather the long widths are exclusively for spurious charge.  That should be
sufficient based on my experience. However, I'm assuming non RC waveshaping.
Remember you want the clock to take off slowly at first and then speed up
towards the end of the rising edge (RC does the opposite). 

By the way, one should see more spurious on the edges of the CCD than its
middle (due to poly resistance and waveshaping in the middle of the CCD).
******jj
 
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 The on-chip amplifiers of LL CCID20 CCDs got non-linear and saturation
 before pixels reaching their full well. We got linear range of amplifier
 only up to 115 ke- (sorry, I should not use "full well" for this)  
 Mingzhi
 -----

*****jj
Might want to look into that nonlinearity problem. I wonder.  . does it have
to do with Lincoln's high sensitivity (ie., 20 uV/e-)? That is, a 2.3 V
change on the gate for 115 k e-. That swing might cause the linearity.
*****jj
 

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 What you mean that "residual image effects in the image you are reading
(i.e.,
 tails)."  Mingzhi
 --------

******jj
Recall you can reach SFW in the image you are reading out (i.e., charge
interacts with surface states). . . The only way to eliminate that is by
inverting.
*****jj

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(1) Is it "high level vertical CTE"?  Mingzhi
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******jj
Yes, it is called Surface Full Well (SFW). Results in deferred charge.
******jj

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 (2) If you mean that it happens because of the special erase clocks.
     why? We setup the special erase clocks 0v to -12v and all
     inverted.  Mingzhi
--------

*****jj 
No
*****jj

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 (3) If you mean that it happens because we do not inverted clocks
     during read out time.

     We have no choice because LL CCDs are not MPP devices and this is why
     we need special inverted erase clocks to remove the residual images.
 Mingzhi
--------


******jj
No, partial inversion (two phases low - one phase high) will eliminate
surface residual image (no need for MPP either). Just make sure the barriers
go into inversion. No special clocks are required.
*******jj

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 Actually we did not see any vertical tail in the images which lower
 than 163 ke- and we saw very sharp residual image pattern even we used
 regular noninverted erase clocks.  Mingzhi
----------

*******jj
Taking barriers out of inversion will drastically reduce full well .. . again
partially inverted (say -8 to +5) will achieve highest full well possible and
eliminate residual image. The only thing to worry about is spurious (use
proper waveshaping here).
********jj
 
 ------
 We are still do optimization of the special erase clocks, such as
 voltages, shape, min. requirest erase time and erase procedure.
 But now we don't worry causing spurious charge and other problem,
 because this optimization is independent.
 MIngzhi
 ------

******jj
? Keep it simple
******jj
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 According to our experiment results: 
 (our vertical clocks already very wide and slow rising edge)
 (1) if we use Vv=2v,-6v for vertical clocks
     we got spurious charge: 0.42e-
     and residual image:   9.16e- (100sec integration time)
 (2) if we use vv=2v,-8v
     we got spurious charge: 6.16e-
     and residual image:   3.5e- (100sec)
 
 if we use special erase clocks:
     we got spurious charge 0.42e-
     and residual image:   1.1e- (100sec)


 Which do you prefer?

*******jj
Always . . . partial inversion to keep things simple and optimum. Take
spurious charge off to the side and work on it. Don't give up ..  you are
down to 6 e-..  a little more waveshaping should do it.
******jj
 
 
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