Parallel clocking issues

[Ralf Kohley]

Hi Roger and all,

we've experimented with finding an optimum setup for the parallel
clocks, which is not that trivial and even slightly different from
device to device of the same kind of CCD.
I tried to summerize some effects in my SPIE 95 article (Vol. 2415).
There are different kinds of full well limitation to be considered:

example: thick Loral 2k x 2k, 15 um

1. Integration full well
   Do you operate in the bloomed or surface full well regime?
   a) Bloomed full well (less positive voltages in upper rail, 
      say between 0 and 1.4 V):
      Blooming occurs before electrons reach the surface (Si-Si02 interface)
      ( < 200000 e- )
   b) Surface full well (more positive voltages in upper rail,
      say between 1.4 and 6 V):
      Blooming occurs at very high values ( >>200000 e-), but electrons
      reach the surface much before. => residual images
   c) Optimum full well
      "intersection of surface and bloomed full well"
      Blooming occurs just at the moment when electrons reach the surface,
      noramlly the best ( 1.4 V leading to 200000 e- capacity )

2. Transport full well (parallel clocks)
   Again, do you operate in the bloomed or surface full well regime?
   Normally during integration on a MPP-CCD, the additionally doped
   phase plays the role as the barrier (-8 V or whatever). During
   transport it also becomes a collecting potential, but the well is
   not as deep as for the other two phases. We found a difference of
   +2.5 V, which we use as an offset for this particular phase. 
   I believe, that most full well limitation arise from transport rather
   then from integration.
   a) Bloomed full well
      Blooming occurs, but no smearing
   b) Surface full well
      No blooming, but smearing of a part of the charge due to bad CTE
      of charge transported along the surface.
   c) Optimum full well
      We reach optimum full well with
         P1:  -8 V   to +1.4 V
         P2:  -8 V   to +1.4 V
         P3:  -5.5 V to +3.9 V

3. Transport full well (parallel transfer gate)
   Are the transfer gates in both directions equally doped?
   If not and you use a fixed voltage for the transfer gates, you can get 
   different full wells in both directions.


On inversion:

I did a test with switching voltages between integration and read-out.
Take a look at http://www.astro.uni-bonn.de/~rkohley/paper/eso96.html

More on spurious charge:


We don't use tri-level clocking during read-out, since the the production
of spurious charge scales with clocking cycles. With optimum full well clocking
and three phases we get a gradient of <0.001 e- per line, i.e for a 2k chip 
<2e- spurious charge in the last row. We only used tri-level clocking for anti-
blooming.
The stronger effect is for sure the reduction of the positive upper rails,
it looks like a factor of 3 every 1.5 V.


Cheers,

   Ralf

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| Ralf Kohley                                   Tel.: +49 228 735658 |
| Sternwarte der Universitaet Bonn              Fax.: +49 228 733672 |
| Auf dem Huegel 71                                                  |
| D-53121 Bonn                                                       |
| Germany                           Email: rkohley at astro.uni-bonn.de |
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