*** The Physical Mechanism Behind Spurious Charge

[MYPIXEL at aol.com]

Posted to CCD-world:
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************jj

This tutorial helps physically explain why spurious charge is generated  . . .
. Paragraph (3) is most important. 

Jim

**************jj

SPURIOUS CHARGE

(1)
Spurious charge is an important source of unwanted charge when CCDs are
clocked into inversion. Under this condition holes from the channel-stops
migrate and collect beneath the gate pinning the surface to the substrate
potential.  Some of these holes become trapped at the Si-SiO2 interface. When
the clock is switched to the noninverted state the holes are accelerated away
from the Si-SiO2 interface. Some holes are released with sufficient energy to
create additional electron-hole pairs by colliding with silicon atoms (a
process known as impact ionization). These "spurious" electrons are then
collected in the nearest potential well.

(2)
Spurious charge was first observed when testing the 800 x 800 virtual phase
CCD for the Galileo project  (the virtual phase CCD inherently inverts for it
to work). The source of charge limited the read noise floor to approximately
100 e- rms,  and therefore, a thorough understanding of the physics involved
behind the problem was undertaken (the noise specification for the Galileo
camera was 20 e - rms). There were numerous findings found in regulating
spurious charge. First, spurious charge is generated on the leading edge of
the clock as a phase comes out of inversion. The falling edge has no influence
on spurious charge generation in CCDs. Second, spurious charge increases
exponentially with clock rise time and clock swing. Sending holes back to the
channel-stops with a fast moving, high amplitude clock increases impact
ionization and spurious charge. Third, spurious charge increases with clock
pulse width (i.e., the time the clock spends in the noninverted state
immediately after coming out of inversion). If  the clock width is relatively
short holes will remain in the interface states reducing impact ionization
(the effect is seen for clock widths less than 100 micro-sec). Forth, spurious
charge increases as the operating temperature of the CCD is reduced  (theory
indicates that impact ionization is more efficient at cold temperatures
because of carrier mobility). Fifth, spurious charge increases linearly on the
number of transfers that take place. Sixth, and the most critical to read
noise performance,  the noise this phenomenon produces can be characterized as
shot noise. In other words,  the noise increases by the square-root of the
spurious charge generated.

	                                 
Example 

	Find the spurious charge generated in each horizontal pixel for a register
that is 1024 pixels long. Assume that 0.1 e- is generated during each pixel
transfer on the average. Also calculate the shot noise produced. Compare the
spurious noise to an on-chip amplifier that exhibits a noise floor of 3 e-.

	Solution:

	For 1024 pixel transfers 107 e-/pixel of spurious charge is collected in each
pixel. The corresponding shot noise is:

		NSC = (107)1/2 

		NSC = 10.3 e- rms

	Note that this noise is considerably greater that the read noise of the on-
chip amplifier.

	                                 	
(3)
The question of why spurious charge is only generated on the rising edge and
not the falling edge is a curious one.  When a phase inverts holes from the
channel stop region populate the surface taking tens of nano-sec to transit
depending on doping characteristics.  The potential difference between the
channel stop and surface potential under a phase is small because each region
is near zero volts when inversion occurs (channel stops are held at ground
potential). Holes therefore flow under low field conditions. However, the
potential difference is considerably greater for some holes when a phase comes
out of inversion. A hole can remain trapped until the surface reaches its
maximum potential (equal to the gate voltage applied + oxide drop). The
electric field generated is equal to the potential difference divided by the
distance the hole travels . For example, an electric field of  10^5 V/cm is
generated for a potential difference of 10 V over a distance of 1 micron. It
is this high electric field that the hole feels that causes impact ionization
and spurious charge. The highest fields are generated near the edges of the
channel stop regions where the potential difference is greatest.
 
(4) 
Spurious charge can be mistaken from normal dark current. The sources can be
measured separately because spurious charge is only generated when the device
is clocked and its amplitude is not a function of integration time. If dark
charge increases with clock amplitude or when driven into inversion then the
source is likely to be spurious charge. It is more difficult to detect
spurious charge in the horizontal register since it will appear as an offset
in each pixel. Horizontal spurious charge is isolated by measuring the read
noise as the clocks are adjusted. If the noise level changes as the clock
level changes then it is likely to be spurious charge. Ideally the horizontal
clocks should not be operated inverted  preventing spurious charge generation.

(5)
Four methods are used to reduce spurious charge to negligible levels. The most
popular method is to simply wave-shape clocks. Waveshaping reduces the
electric fields and returns the holes to the channel-stop regions at a slower
rate thereby suppressing spurious charge. Waveshaping can be implemented by
adding a R-C network in series with the output of each CCD clock driver. The
amount of waveshaping is  maximized by allowing a phase to settle 3 time
constants during the clock over-lap period. The second method used to reduce
spurious charge is to limit the positive excursion of the clocks  (and
therefore electric fields) without degrading full well performance (i.e,
maintain BFW = SFW).. Third, the trapped holes can also be ameliorated by use
of a tri-level clocking scheme. This technique uses a intermediate clocking
voltage, which lies between the high and low clock rails required for complete
charge transfer at voltage level which is just slightly above the inverted
state. The rising edge of the transition from the lowest voltage to the
intermediate voltage remains as long as possible to allow holes to return to
channel stops (how long one can actually stay at this level depends on the
pixel rate). After this period of time charge is transferred by a short
positive going pulse. Tri-level clocking was first implemented in driving the
horizontal register for the Galileo CCD allowing the read noise to meet
specification. The forth method utilizes narrow clock pulses. As mentioned
above, holes are detrapped during a specific period of time (on the order of
several micro-seconds at room temperature). Therefore, transferring signal
charge  and returning the phase back to inversion quickly reduces spurious
charge. This particular scheme is useful for high speed applications.
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