CCD-world: High Speed Erasure

[MYPIXEL at aol.com]

The following was posted to CCD-world:

In a message dated 2/12/00 7:57:54 AM EST, zzwang at class1.bao.ac.cn writes:

<< The following was posted to CCD-world:
 
 Dear Colleagues,
 
 I want to design a CCD controller with TH7899 Thomson 2048x2048 chip.
 I hope fast clean CCD less than 100ms. Who have used such CCD and 
 how to design the timing is better?

***************************jj
Zhaowang,

"High speed erasure" for multi-phase CCDs without a dump drain.. . .  . .

It is best to take the vertical clocks to a lower potential (typically 
inverted) than the horizontal clocks (typically a few volts above inversion). 
This will allow the horizontal register to act as a drain and prevent "charge 
backup" problems into the array during high speed erasure. Charge will bloom 
in the horizontal register and leave the reset switch under these bias 
conditions. Erasures times < 10 ms have been acheived for conventional 1024 x 
1024 mulit-phase CCDs under full well conditions. This operating mode is 
working well  for the Cassini mission where high speed erasure is required 
for the 1024 x 1024 three-phase CCDs on board.

Jim
*******************************jj 




 Best Regards
 
 Zhaowang Zhao
 Beijing Astronomical Observatory
 Datun Rd. #20A
 Chaoyang District
 Beijing  100012
 China
 zzwang at class1.bao.ac.cn >>
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